📄 ram_control.tan.rpt
字号:
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3 ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg2 ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg2 ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg1 ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg1 ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg0 ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg0 ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 224.92 MHz ( period = 4.446 ns ) ; countwr[1] ; wren ; clk ; clk ; None ; None ; 4.185 ns ;
; N/A ; 226.19 MHz ( period = 4.421 ns ) ; countwr[1] ; state.STATE2 ; clk ; clk ; None ; None ; 4.160 ns ;
; N/A ; 233.26 MHz ( period = 4.287 ns ) ; countwr[0] ; wren ; clk ; clk ; None ; None ; 4.026 ns ;
; N/A ; 234.63 MHz ( period = 4.262 ns ) ; countwr[0] ; state.STATE2 ; clk ; clk ; None ; None ; 4.001 ns ;
; N/A ; 239.29 MHz ( period = 4.179 ns ) ; countwr[2] ; wren ; clk ; clk ; None ; None ; 3.918 ns ;
; N/A ; 240.73 MHz ( period = 4.154 ns ) ; countwr[2] ; state.STATE2 ; clk ; clk ; None ; None ; 3.893 ns ;
; N/A ; 248.14 MHz ( period = 4.030 ns ) ; countwr[1] ; rdaddress[2] ; clk ; clk ; None ; None ; 3.769 ns ;
; N/A ; 251.64 MHz ( period = 3.974 ns ) ; countwr[3] ; wren ; clk ; clk ; None ; None ; 3.713 ns ;
; N/A ; 253.23 MHz ( period = 3.949 ns ) ; countwr[3] ; state.STATE2 ; clk ; clk ; None ; None ; 3.688 ns ;
; N/A ; 254.13 MHz ( period = 3.935 ns ) ; state.STATE2 ; rdaddress[2] ; clk ; clk ; None ; None ; 3.674 ns ;
; N/A ; 258.33 MHz ( period = 3.871 ns ) ; countwr[0] ; rdaddress[2] ; clk ; clk ; None ; None ; 3.610 ns ;
; N/A ; 265.75 MHz ( period = 3.763 ns ) ; countwr[2] ; rdaddress[2] ; clk ; clk ; None ; None ; 3.502 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[3] ; rdaddress[2] ; clk ; clk ; None ; None ; 3.297 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2 ; state.STATE2 ; clk ; clk ; None ; None ; 3.078 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[1] ; rdaddress[3] ; clk ; clk ; None ; None ; 3.027 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[1] ; rdaddress[1] ; clk ; clk ; None ; None ; 3.027 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[1] ; rdaddress[0] ; clk ; clk ; None ; None ; 3.027 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[4] ; rdaddress[2] ; clk ; clk ; None ; None ; 2.946 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2 ; rdaddress[3] ; clk ; clk ; None ; None ; 2.932 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2 ; rdaddress[1] ; clk ; clk ; None ; None ; 2.932 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2 ; rdaddress[0] ; clk ; clk ; None ; None ; 2.932 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[0] ; rdaddress[3] ; clk ; clk ; None ; None ; 2.868 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[0] ; rdaddress[1] ; clk ; clk ; None ; None ; 2.868 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[0] ; rdaddress[0] ; clk ; clk ; None ; None ; 2.868 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2 ; countwr[4] ; clk ; clk ; None ; None ; 2.766 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[2] ; rdaddress[3] ; clk ; clk ; None ; None ; 2.760 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[2] ; rdaddress[1] ; clk ; clk ; None ; None ; 2.760 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[2] ; rdaddress[0] ; clk ; clk ; None ; None ; 2.760 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2 ; countwr[3] ; clk ; clk ; None ; None ; 2.686 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2 ; wraddress[3] ; clk ; clk ; None ; None ; 2.674 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2 ; data[2] ; clk ; clk ; None ; None ; 2.674 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2 ; data[1] ; clk ; clk ; None ; None ; 2.674 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2 ; data[0] ; clk ; clk ; None ; None ; 2.674 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2 ; countwr[2] ; clk ; clk ; None ; None ; 2.606 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[3] ; rdaddress[3] ; clk ; clk ; None ; None ; 2.555 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[3] ; rdaddress[1] ; clk ; clk ; None ; None ; 2.555 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[3] ; rdaddress[0] ; clk ; clk ; None ; None ; 2.555 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[4] ; wren ; clk ; clk ; None ; None ; 2.541 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2 ; countwr[1] ; clk ; clk ; None ; None ; 2.526 ns ;
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