ram_control.vo

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// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

// DATE "07/29/2006 11:10:31"

// 
// Device: Altera EP1C6Q240C8 Package PQFP240
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module 	ram_control (
	clk,
	rst,
	q);
input 	clk;
input 	rst;
output 	[3:0] q;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("ram_control_v.sdo");
// synopsys translate_on

wire \clk~combout ;
wire \rst~combout ;
wire \countwr[0] ;
wire \countwr[0]~131COUT1_147 ;
wire \countwr[1]~135 ;
wire \countwr[1]~135COUT1 ;
wire \countwr[2] ;
wire \countwr[2]~139 ;
wire \countwr[2]~139COUT1_148 ;
wire \countwr[3] ;
wire \countwr[3]~143 ;
wire \countwr[3]~143COUT1_149 ;
wire \countwr[4] ;
wire \state~122 ;
wire \state.STATE2 ;
wire \countwr[0]~131 ;
wire \countwr[1] ;
wire \reduce_nor~22 ;
wire \reduce_nor~0 ;
wire \reduce_nor~1 ;
wire wren;
wire \data[0]~61 ;
wire \data[0] ;
wire \data[1] ;
wire \data[2] ;
wire \wraddress[3] ;
wire \rdaddress[0]~90 ;
wire \rdaddress[0] ;
wire \rdaddress[1] ;
wire \rdaddress[2] ;
wire \rdaddress[3] ;
wire \RAM_36|altsyncram_component|auto_generated|q_b[0] ;
wire \RAM_36|altsyncram_component|auto_generated|q_b[1] ;
wire \RAM_36|altsyncram_component|auto_generated|q_b[2] ;
wire \RAM_36|altsyncram_component|auto_generated|q_b[3] ;

wire [3:0] \RAM_36|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;

assign \RAM_36|altsyncram_component|auto_generated|q_b[0]  = \RAM_36|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];
assign \RAM_36|altsyncram_component|auto_generated|q_b[1]  = \RAM_36|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [1];
assign \RAM_36|altsyncram_component|auto_generated|q_b[2]  = \RAM_36|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [2];
assign \RAM_36|altsyncram_component|auto_generated|q_b[3]  = \RAM_36|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [3];

// atom is at PIN_29
cyclone_io \clk~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.padio(clk));
// synopsys translate_off
defparam \clk~I .operation_mode = "input";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .output_sync_reset = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PIN_85
cyclone_io \rst~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rst~combout ),
	.regout(),
	.padio(rst));
// synopsys translate_off
defparam \rst~I .operation_mode = "input";
defparam \rst~I .input_register_mode = "none";
defparam \rst~I .output_register_mode = "none";
defparam \rst~I .oe_register_mode = "none";
defparam \rst~I .input_async_reset = "none";
defparam \rst~I .output_async_reset = "none";
defparam \rst~I .oe_async_reset = "none";
defparam \rst~I .input_sync_reset = "none";
defparam \rst~I .output_sync_reset = "none";
defparam \rst~I .oe_sync_reset = "none";
defparam \rst~I .input_power_up = "low";
defparam \rst~I .output_power_up = "low";
defparam \rst~I .oe_power_up = "low";
// synopsys translate_on

// atom is at LC_X14_Y2_N0
cyclone_lcell \countwr[0]~I (
// Equation(s):
// \countwr[0]  = DFFEAS(\state.STATE2  $ !\countwr[0] , GLOBAL(\clk~combout ), VCC, , , , , !\rst~combout , )
// \countwr[0]~131  = CARRY(!\state.STATE2  & \countwr[0] )
// \countwr[0]~131COUT1_147  = CARRY(!\state.STATE2  & \countwr[0] )

	.clk(\clk~combout ),
	.dataa(\state.STATE2 ),
	.datab(\countwr[0] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(!\rst~combout ),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\countwr[0] ),
	.cout(),
	.cout0(\countwr[0]~131 ),
	.cout1(\countwr[0]~131COUT1_147 ));
// synopsys translate_off
defparam \countwr[0]~I .operation_mode = "arithmetic";
defparam \countwr[0]~I .synch_mode = "on";
defparam \countwr[0]~I .register_cascade_mode = "off";
defparam \countwr[0]~I .sum_lutc_input = "datac";
defparam \countwr[0]~I .lut_mask = "9944";
defparam \countwr[0]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X14_Y2_N1
cyclone_lcell \countwr[1]~I (
// Equation(s):
// \countwr[1]  = DFFEAS(\countwr[1]  $ (\countwr[0]~131 ), GLOBAL(\clk~combout ), VCC, , , , , !\rst~combout , )
// \countwr[1]~135  = CARRY(!\countwr[0]~131  # !\countwr[1] )
// \countwr[1]~135COUT1  = CARRY(!\countwr[0]~131COUT1_147  # !\countwr[1] )

	.clk(\clk~combout ),
	.dataa(\countwr[1] ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(!\rst~combout ),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\countwr[0]~131 ),
	.cin1(\countwr[0]~131COUT1_147 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\countwr[1] ),
	.cout(),
	.cout0(\countwr[1]~135 ),
	.cout1(\countwr[1]~135COUT1 ));
// synopsys translate_off
defparam \countwr[1]~I .operation_mode = "arithmetic";
defparam \countwr[1]~I .synch_mode = "on";
defparam \countwr[1]~I .register_cascade_mode = "off";
defparam \countwr[1]~I .sum_lutc_input = "cin";
defparam \countwr[1]~I .lut_mask = "5A5F";
defparam \countwr[1]~I .cin0_used = "true";
defparam \countwr[1]~I .cin1_used = "true";
defparam \countwr[1]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X14_Y2_N2
cyclone_lcell \countwr[2]~I (
// Equation(s):
// \countwr[2]  = DFFEAS(\countwr[2]  $ (!\countwr[1]~135 ), GLOBAL(\clk~combout ), VCC, , , , , !\rst~combout , )
// \countwr[2]~139  = CARRY(\countwr[2]  & (!\countwr[1]~135 ))
// \countwr[2]~139COUT1_148  = CARRY(\countwr[2]  & (!\countwr[1]~135COUT1 ))

	.clk(\clk~combout ),
	.dataa(\countwr[2] ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(!\rst~combout ),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\countwr[1]~135 ),
	.cin1(\countwr[1]~135COUT1 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\countwr[2] ),
	.cout(),
	.cout0(\countwr[2]~139 ),
	.cout1(\countwr[2]~139COUT1_148 ));
// synopsys translate_off
defparam \countwr[2]~I .operation_mode = "arithmetic";
defparam \countwr[2]~I .synch_mode = "on";
defparam \countwr[2]~I .register_cascade_mode = "off";
defparam \countwr[2]~I .sum_lutc_input = "cin";
defparam \countwr[2]~I .lut_mask = "A50A";
defparam \countwr[2]~I .cin0_used = "true";
defparam \countwr[2]~I .cin1_used = "true";
defparam \countwr[2]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X14_Y2_N3
cyclone_lcell \countwr[3]~I (
// Equation(s):
// \countwr[3]  = DFFEAS(\countwr[3]  $ \countwr[2]~139 , GLOBAL(\clk~combout ), VCC, , , , , !\rst~combout , )
// \countwr[3]~143  = CARRY(!\countwr[2]~139  # !\countwr[3] )
// \countwr[3]~143COUT1_149  = CARRY(!\countwr[2]~139COUT1_148  # !\countwr[3] )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(\countwr[3] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(!\rst~combout ),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\countwr[2]~139 ),
	.cin1(\countwr[2]~139COUT1_148 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\countwr[3] ),
	.cout(),
	.cout0(\countwr[3]~143 ),
	.cout1(\countwr[3]~143COUT1_149 ));
// synopsys translate_off
defparam \countwr[3]~I .operation_mode = "arithmetic";
defparam \countwr[3]~I .synch_mode = "on";
defparam \countwr[3]~I .register_cascade_mode = "off";
defparam \countwr[3]~I .sum_lutc_input = "cin";
defparam \countwr[3]~I .lut_mask = "3C3F";
defparam \countwr[3]~I .cin0_used = "true";
defparam \countwr[3]~I .cin1_used = "true";
defparam \countwr[3]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X14_Y2_N4
cyclone_lcell \countwr[4]~I (
// Equation(s):
// \countwr[4]  = DFFEAS(\countwr[4]  $ !\countwr[3]~143 , GLOBAL(\clk~combout ), VCC, , , , , !\rst~combout , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(\countwr[4] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(!\rst~combout ),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\countwr[3]~143 ),
	.cin1(\countwr[3]~143COUT1_149 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\countwr[4] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \countwr[4]~I .operation_mode = "normal";
defparam \countwr[4]~I .synch_mode = "on";
defparam \countwr[4]~I .register_cascade_mode = "off";
defparam \countwr[4]~I .sum_lutc_input = "cin";
defparam \countwr[4]~I .lut_mask = "C3C3";
defparam \countwr[4]~I .cin0_used = "true";
defparam \countwr[4]~I .cin1_used = "true";
defparam \countwr[4]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X16_Y2_N9
cyclone_lcell \state~122_I (
// Equation(s):
// \state~122  = !\state.STATE2  & \reduce_nor~22  # !\rst~combout 

	.clk(gnd),
	.dataa(\state.STATE2 ),
	.datab(vcc),
	.datac(\rst~combout ),
	.datad(\reduce_nor~22 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),