ram_control.fit.summary

FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！

Flow Status : Successful - Sat Jul 29 11:10:21 2006
Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version
Revision Name : ram_control
Top-level Entity Name : ram_control
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 21 / 5,980 ( < 1 % )
Total pins : 6 / 185 ( 3 % )
Total virtual pins : 0
Total memory bits : 64 / 92,160 ( < 1 % )
Total PLLs : 0 / 2 ( 0 % )