ram_control.map.eqn

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-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- applicable agreement for further details.
--D1_q_b[0] is RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 16, Port A Width: 1, Port B Depth: 16, Port B Width: 1
--Port A Logical Depth: 16, Port A Logical Width: 4, Port B Logical Depth: 16, Port B Logical Width: 4
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
D1_q_b[0]_PORT_A_data_in = data[0];
D1_q_b[0]_PORT_A_data_in_reg = DFFE(D1_q_b[0]_PORT_A_data_in, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_A_address = BUS(data[0], data[1], data[2], wraddress[3]);
D1_q_b[0]_PORT_A_address_reg = DFFE(D1_q_b[0]_PORT_A_address, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3]);
D1_q_b[0]_PORT_B_address_reg = DFFE(D1_q_b[0]_PORT_B_address, D1_q_b[0]_clock_1, , , );
D1_q_b[0]_PORT_A_write_enable = VCC;
D1_q_b[0]_PORT_A_write_enable_reg = DFFE(D1_q_b[0]_PORT_A_write_enable, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_B_read_enable = VCC;
D1_q_b[0]_PORT_B_read_enable_reg = DFFE(D1_q_b[0]_PORT_B_read_enable, D1_q_b[0]_clock_1, , , );
D1_q_b[0]_clock_0 = clk;
D1_q_b[0]_clock_1 = clk;
D1_q_b[0]_clock_enable_0 = wren;
D1_q_b[0]_PORT_B_data_out = MEMORY(D1_q_b[0]_PORT_A_data_in_reg, , D1_q_b[0]_PORT_A_address_reg, D1_q_b[0]_PORT_B_address_reg, D1_q_b[0]_PORT_A_write_enable_reg, D1_q_b[0]_PORT_B_read_enable_reg, , , D1_q_b[0]_clock_0, D1_q_b[0]_clock_1, D1_q_b[0]_clock_enable_0, , , );
D1_q_b[0] = D1_q_b[0]_PORT_B_data_out[0];


--D1_q_b[1] is RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 16, Port A Width: 1, Port B Depth: 16, Port B Width: 1
--Port A Logical Depth: 16, Port A Logical Width: 4, Port B Logical Depth: 16, Port B Logical Width: 4
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
D1_q_b[1]_PORT_A_data_in = data[1];
D1_q_b[1]_PORT_A_data_in_reg = DFFE(D1_q_b[1]_PORT_A_data_in, D1_q_b[1]_clock_0, , , D1_q_b[1]_clock_enable_0);
D1_q_b[1]_PORT_A_address = BUS(data[0], data[1], data[2], wraddress[3]);
D1_q_b[1]_PORT_A_address_reg = DFFE(D1_q_b[1]_PORT_A_address, D1_q_b[1]_clock_0, , , D1_q_b[1]_clock_enable_0);
D1_q_b[1]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3]);
D1_q_b[1]_PORT_B_address_reg = DFFE(D1_q_b[1]_PORT_B_address, D1_q_b[1]_clock_1, , , );
D1_q_b[1]_PORT_A_write_enable = VCC;
D1_q_b[1]_PORT_A_write_enable_reg = DFFE(D1_q_b[1]_PORT_A_write_enable, D1_q_b[1]_clock_0, , , D1_q_b[1]_clock_enable_0);
D1_q_b[1]_PORT_B_read_enable = VCC;
D1_q_b[1]_PORT_B_read_enable_reg = DFFE(D1_q_b[1]_PORT_B_read_enable, D1_q_b[1]_clock_1, , , );
D1_q_b[1]_clock_0 = clk;
D1_q_b[1]_clock_1 = clk;
D1_q_b[1]_clock_enable_0 = wren;
D1_q_b[1]_PORT_B_data_out = MEMORY(D1_q_b[1]_PORT_A_data_in_reg, , D1_q_b[1]_PORT_A_address_reg, D1_q_b[1]_PORT_B_address_reg, D1_q_b[1]_PORT_A_write_enable_reg, D1_q_b[1]_PORT_B_read_enable_reg, , , D1_q_b[1]_clock_0, D1_q_b[1]_clock_1, D1_q_b[1]_clock_enable_0, , , );
D1_q_b[1] = D1_q_b[1]_PORT_B_data_out[0];


--D1_q_b[2] is RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 16, Port A Width: 1, Port B Depth: 16, Port B Width: 1
--Port A Logical Depth: 16, Port A Logical Width: 4, Port B Logical Depth: 16, Port B Logical Width: 4
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
D1_q_b[2]_PORT_A_data_in = data[2];
D1_q_b[2]_PORT_A_data_in_reg = DFFE(D1_q_b[2]_PORT_A_data_in, D1_q_b[2]_clock_0, , , D1_q_b[2]_clock_enable_0);
D1_q_b[2]_PORT_A_address = BUS(data[0], data[1], data[2], wraddress[3]);
D1_q_b[2]_PORT_A_address_reg = DFFE(D1_q_b[2]_PORT_A_address, D1_q_b[2]_clock_0, , , D1_q_b[2]_clock_enable_0);
D1_q_b[2]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3]);
D1_q_b[2]_PORT_B_address_reg = DFFE(D1_q_b[2]_PORT_B_address, D1_q_b[2]_clock_1, , , );
D1_q_b[2]_PORT_A_write_enable = VCC;
D1_q_b[2]_PORT_A_write_enable_reg = DFFE(D1_q_b[2]_PORT_A_write_enable, D1_q_b[2]_clock_0, , , D1_q_b[2]_clock_enable_0);
D1_q_b[2]_PORT_B_read_enable = VCC;
D1_q_b[2]_PORT_B_read_enable_reg = DFFE(D1_q_b[2]_PORT_B_read_enable, D1_q_b[2]_clock_1, , , );
D1_q_b[2]_clock_0 = clk;
D1_q_b[2]_clock_1 = clk;
D1_q_b[2]_clock_enable_0 = wren;
D1_q_b[2]_PORT_B_data_out = MEMORY(D1_q_b[2]_PORT_A_data_in_reg, , D1_q_b[2]_PORT_A_address_reg, D1_q_b[2]_PORT_B_address_reg, D1_q_b[2]_PORT_A_write_enable_reg, D1_q_b[2]_PORT_B_read_enable_reg, , , D1_q_b[2]_clock_0, D1_q_b[2]_clock_1, D1_q_b[2]_clock_enable_0, , , );
D1_q_b[2] = D1_q_b[2]_PORT_B_data_out[0];


--D1_q_b[3] is RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 16, Port A Width: 1, Port B Depth: 16, Port B Width: 1
--Port A Logical Depth: 16, Port A Logical Width: 4, Port B Logical Depth: 16, Port B Logical Width: 4
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
D1_q_b[3]_PORT_A_data_in = wraddress[3];
D1_q_b[3]_PORT_A_data_in_reg = DFFE(D1_q_b[3]_PORT_A_data_in, D1_q_b[3]_clock_0, , , D1_q_b[3]_clock_enable_0);
D1_q_b[3]_PORT_A_address = BUS(data[0], data[1], data[2], wraddress[3]);
D1_q_b[3]_PORT_A_address_reg = DFFE(D1_q_b[3]_PORT_A_address, D1_q_b[3]_clock_0, , , D1_q_b[3]_clock_enable_0);
D1_q_b[3]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3]);
D1_q_b[3]_PORT_B_address_reg = DFFE(D1_q_b[3]_PORT_B_address, D1_q_b[3]_clock_1, , , );
D1_q_b[3]_PORT_A_write_enable = VCC;
D1_q_b[3]_PORT_A_write_enable_reg = DFFE(D1_q_b[3]_PORT_A_write_enable, D1_q_b[3]_clock_0, , , D1_q_b[3]_clock_enable_0);
D1_q_b[3]_PORT_B_read_enable = VCC;
D1_q_b[3]_PORT_B_read_enable_reg = DFFE(D1_q_b[3]_PORT_B_read_enable, D1_q_b[3]_clock_1, , , );
D1_q_b[3]_clock_0 = clk;
D1_q_b[3]_clock_1 = clk;
D1_q_b[3]_clock_enable_0 = wren;
D1_q_b[3]_PORT_B_data_out = MEMORY(D1_q_b[3]_PORT_A_data_in_reg, , D1_q_b[3]_PORT_A_address_reg, D1_q_b[3]_PORT_B_address_reg, D1_q_b[3]_PORT_A_write_enable_reg, D1_q_b[3]_PORT_B_read_enable_reg, , , D1_q_b[3]_clock_0, D1_q_b[3]_clock_1, D1_q_b[3]_clock_enable_0, , , );
D1_q_b[3] = D1_q_b[3]_PORT_B_data_out[0];


--wren is wren
--operation mode is normal

wren_lut_out = state.STATE2 & wren # !state.STATE2 & (wren & A1L92 # !A1L82);
wren = DFFEAS(wren_lut_out, clk, VCC, , , , , !rst, );


--data[0] is data[0]
--operation mode is normal

data[0]_lut_out = countwr[0] & rst;
data[0] = DFFEAS(data[0]_lut_out, clk, VCC, , A1L41, , , , );


--data[1] is data[1]
--operation mode is normal

data[1]_lut_out = countwr[1] & rst;
data[1] = DFFEAS(data[1]_lut_out, clk, VCC, , A1L41, , , , );


--data[2] is data[2]
--operation mode is normal

data[2]_lut_out = countwr[2] & rst;
data[2] = DFFEAS(data[2]_lut_out, clk, VCC, , A1L41, , , , );


--wraddress[3] is wraddress[3]
--operation mode is normal

wraddress[3]_lut_out = countwr[3] & rst;
wraddress[3] = DFFEAS(wraddress[3]_lut_out, clk, VCC, , A1L41, , , , );


--rdaddress[0] is rdaddress[0]
--operation mode is normal

rdaddress[0]_lut_out = !rdaddress[0] & (rst);
rdaddress[0] = DFFEAS(rdaddress[0]_lut_out, clk, VCC, , A1L42, , , , );


--rdaddress[1] is rdaddress[1]
--operation mode is normal

rdaddress[1]_lut_out = rdaddress[0] $ rdaddress[1];
rdaddress[1] = DFFEAS(rdaddress[1]_lut_out, clk, VCC, , A1L42, , , !rst, );


--rdaddress[2] is rdaddress[2]
--operation mode is normal

rdaddress[2]_lut_out = rdaddress[2] $ (rdaddress[0] & (rdaddress[1]));
rdaddress[2] = DFFEAS(rdaddress[2]_lut_out, clk, VCC, , A1L42, , , !rst, );


--rdaddress[3] is rdaddress[3]
--operation mode is normal

rdaddress[3]_lut_out = rdaddress[3] $ (rdaddress[2] & rdaddress[0] & rdaddress[1]);
rdaddress[3] = DFFEAS(rdaddress[3]_lut_out, clk, VCC, , A1L42, , , !rst, );


--countwr[4] is countwr[4]
--operation mode is normal

countwr[4]_carry_eqn = A1L01;
countwr[4]_lut_out = countwr[4] $ (!countwr[4]_carry_eqn);
countwr[4] = DFFEAS(countwr[4]_lut_out, clk, VCC, , , , , !rst, );


--countwr[0] is countwr[0]
--operation mode is arithmetic

countwr[0]_lut_out = state.STATE2 $ !countwr[0];
countwr[0] = DFFEAS(countwr[0]_lut_out, clk, VCC, , , , , !rst, );

--A1L4 is countwr[0]~131
--operation mode is arithmetic

A1L4 = CARRY(!state.STATE2 & countwr[0]);


--countwr[1] is countwr[1]
--operation mode is arithmetic

countwr[1]_carry_eqn = A1L4;
countwr[1]_lut_out = countwr[1] $ (countwr[1]_carry_eqn);
countwr[1] = DFFEAS(countwr[1]_lut_out, clk, VCC, , , , , !rst, );

--A1L6 is countwr[1]~135
--operation mode is arithmetic

A1L6 = CARRY(!A1L4 # !countwr[1]);


--countwr[2] is countwr[2]
--operation mode is arithmetic

countwr[2]_carry_eqn = A1L6;
countwr[2]_lut_out = countwr[2] $ (!countwr[2]_carry_eqn);
countwr[2] = DFFEAS(countwr[2]_lut_out, clk, VCC, , , , , !rst, );

--A1L8 is countwr[2]~139
--operation mode is arithmetic

A1L8 = CARRY(countwr[2] & (!A1L6));


--countwr[3] is countwr[3]
--operation mode is arithmetic

countwr[3]_carry_eqn = A1L8;
countwr[3]_lut_out = countwr[3] $ (countwr[3]_carry_eqn);
countwr[3] = DFFEAS(countwr[3]_lut_out, clk, VCC, , , , , !rst, );

--A1L01 is countwr[3]~143
--operation mode is arithmetic

A1L01 = CARRY(!A1L8 # !countwr[3]);


--A1L03 is reduce_nor~22
--operation mode is normal

A1L03 = !countwr[0] & !countwr[1] & !countwr[2] & !countwr[3];


--A1L92 is reduce_nor~1
--operation mode is normal

A1L92 = !A1L03 # !countwr[4];


--A1L82 is reduce_nor~0
--operation mode is normal

A1L82 = countwr[4] # !A1L03;


--state.STATE2 is state.STATE2
--operation mode is normal

state.STATE2_lut_out = rst & (countwr[4] # !A1L03);
state.STATE2 = DFFEAS(state.STATE2_lut_out, clk, VCC, , A1L33, , , , );


--A1L41 is data[0]~61
--operation mode is normal

A1L41 = !rst # !state.STATE2;


--A1L42 is rdaddress[0]~90
--operation mode is normal

A1L42 = state.STATE2 # countwr[4] & A1L03 # !rst;


--A1L33 is state~122
--operation mode is normal

A1L33 = !state.STATE2 & (A1L03) # !rst;


--clk is clk
--operation mode is input

clk = INPUT();


--rst is rst
--operation mode is input

rst = INPUT();


--q[0] is q[0]
--operation mode is output

q[0] = OUTPUT(D1_q_b[0]);


--q[1] is q[1]
--operation mode is output

q[1] = OUTPUT(D1_q_b[1]);


--q[2] is q[2]
--operation mode is output

q[2] = OUTPUT(D1_q_b[2]);


--q[3] is q[3]
--operation mode is output

q[3] = OUTPUT(D1_q_b[3]);