ram_control.fit.rpt

FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！

;      - state~122       ; 0                 ; ON      ;
+------------------------+-------------------+---------+


+------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                            ;
+-----------------+--------------+---------+--------------+--------+----------------------+------------------+
; Name            ; Location     ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ;
+-----------------+--------------+---------+--------------+--------+----------------------+------------------+
; clk             ; PIN_29       ; 16      ; Clock        ; yes    ; Global clock         ; GCLK3            ;
; data[0]~61      ; LC_X16_Y2_N2 ; 4       ; Clock enable ; no     ; --                   ; --               ;
; rdaddress[0]~90 ; LC_X14_Y2_N9 ; 4       ; Clock enable ; no     ; --                   ; --               ;
; rst             ; PIN_85       ; 18      ; Sync. clear  ; no     ; --                   ; --               ;
; state~122       ; LC_X16_Y2_N9 ; 1       ; Clock enable ; no     ; --                   ; --               ;
; wren            ; LC_X16_Y2_N5 ; 2       ; Clock enable ; no     ; --                   ; --               ;
+-----------------+--------------+---------+--------------+--------+----------------------+------------------+


+---------------------------------------------------------------------+
; Global & Other Fast Signals                                         ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; clk  ; PIN_29   ; 16      ; Global clock         ; GCLK3            ;
+------+----------+---------+----------------------+------------------+


+-----------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals                                                               ;
+-------------------------------------------------------------------------------------+---------+
; Name                                                                                ; Fan-Out ;
+-------------------------------------------------------------------------------------+---------+
; rst                                                                                 ; 18      ;
; state.STATE2                                                                        ; 5       ;
; reduce_nor~22                                                                       ; 5       ;
; countwr[4]                                                                          ; 5       ;
; rdaddress[0]                                                                        ; 5       ;
; rdaddress[0]~90                                                                     ; 4       ;
; data[0]~61                                                                          ; 4       ;
; rdaddress[1]                                                                        ; 4       ;
; countwr[3]                                                                          ; 3       ;
; countwr[2]                                                                          ; 3       ;
; countwr[1]                                                                          ; 3       ;
; countwr[0]                                                                          ; 3       ;
; rdaddress[2]                                                                        ; 3       ;
; rdaddress[3]                                                                        ; 2       ;
; wraddress[3]                                                                        ; 2       ;
; data[2]                                                                             ; 2       ;
; data[1]                                                                             ; 2       ;
; data[0]                                                                             ; 2       ;
; wren                                                                                ; 2       ;
; state~122                                                                           ; 1       ;
; reduce_nor~0                                                                        ; 1       ;
; reduce_nor~1                                                                        ; 1       ;
; countwr[3]~143COUT1_149                                                             ; 1       ;
; countwr[3]~143                                                                      ; 1       ;
; countwr[2]~139COUT1_148                                                             ; 1       ;
; countwr[2]~139                                                                      ; 1       ;
; countwr[1]~135COUT1                                                                 ; 1       ;
; countwr[1]~135                                                                      ; 1       ;
; countwr[0]~131COUT1_147                                                             ; 1       ;
; countwr[0]~131                                                                      ; 1       ;
; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[1] ; 1       ;
; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[2] ; 1       ;
; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[3] ; 1       ;
; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[0] ; 1       ;
+-------------------------------------------------------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+---------------------+------+------+------------+
; Name                                                                                    ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Bits ; M4Ks ; MIF  ; Location   ;
+-----------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+---------------------+------+------+------------+
; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16           ; 4            ; 16           ; 4            ; yes                    ; no                      ; yes                    ; no                      ; 64   ; 64                  ; 1    ; None ; M4K_X17_Y2 ;
+-----------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+---------------------+------+------+------------+


+----------------------------------------------------+
; Interconnect Usage Summary                         ;
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage                 ;
+----------------------------+-----------------------+
; C4s                        ; 5 / 16,320 ( < 1 % )  ;
; Direct links               ; 9 / 21,944 ( < 1 % )  ;
; Global clocks              ; 1 / 8 ( 12 % )        ;
; LAB clocks                 ; 2 / 240 ( < 1 % )     ;
; LUT chains                 ; 0 / 5,382 ( 0 % )     ;
; Local interconnects        ; 37 / 21,944 ( < 1 % ) ;
; M4K buffers                ; 4 / 720 ( < 1 % )     ;
; R4s                        ; 17 / 14,640 ( < 1 % ) ;
+----------------------------+-----------------------+


+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 7.00) ; Number of LABs  (Total = 3) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 0                           ;
; 2                                          ; 0                           ;
; 3                                          ; 0                           ;
; 4                                          ; 0                           ;
; 5                                          ; 1                           ;
; 6                                          ; 1                           ;
; 7                                          ; 0                           ;
; 8                                          ; 0                           ;
; 9                                          ; 0                           ;
; 10                                         ; 1                           ;
+--------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 2.00) ; Number of LABs  (Total = 3) ;
+------------------------------------+-----------------------------+
; 1 Clock                            ; 3                           ;
; 1 Clock enable                     ; 1                           ;
; 1 Sync. clear                      ; 1                           ;
; 2 Clock enables                    ; 1                           ;
+------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 7.00) ; Number of LABs  (Total = 3) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 0                           ;
; 3