chuankourom.mif

FPGA串口界面调试程序,用VHDL语言实现

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- Quartus II generated Memory Initialization File (.mif)

WIDTH=1;
DEPTH=63;

ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;

CONTENT BEGIN
	0   :   1;
	[1..2]  :   0;
	3   :   1;
	4   :   0;
	5   :   1;
	6   :   0;
	7   :   1;
	8   :   0;
	[9..10]  :   1;
	11  :   0;
	12  :   1;
	13  :   0;
	14  :   1;
	15  :   0;
	16  :   1;
	17  :   0;
	18  :   1;
	19  :   0;
	20  :   1;
	21  :   0;
	22  :   1;
	[23..29]  :   0;
	30  :   1;
	31  :   0;
	32  :   1;
	33  :   0;
	34  :   1;
	[35..39]  :   0;
	40  :   1;
	[41..42]  :   0;
	[43..44]  :   1;
	[45..49]  :   0;
	[50..62]  :   1;
END;