test.map.eqn

FPGA串口界面调试程序,用VHDL语言实现

B1L904 = B1_count1_1[4] & B1_count1_1[3] & B1_count1_1[0];


--B1L804 is rs422:inst|temp[4]~3
--operation mode is normal

B1L804 = B1_count1_1[2] & B1L504 & B1L993 & B1L904;


--B1L604 is rs422:inst|temp[3]~304
--operation mode is normal

B1L604 = !B1_count1_1[4] & !B1_count1_1[3] & !B1_count1_1[0];


--B1L404 is rs422:inst|temp[3]~4
--operation mode is normal

B1L404 = B1_count1_1[2] & B1L504 & B1L993 & B1L604;


--B1L104 is rs422:inst|temp[2]~305
--operation mode is normal

B1L104 = B1_count1_1[6] & (!B1_count1_1[4] & !B1_count1_1[2]);


--B1L204 is rs422:inst|temp[2]~306
--operation mode is normal

B1L204 = B1_count1_1[1] & B1L104 & B1L783 & B1L583;


--B1L693 is rs422:inst|temp[1]~6
--operation mode is normal

B1L693 = B1L793 & B1L893 & B1L993 & !B1_count1_1[2];


--B1L493 is rs422:inst|temp[0]~307
--operation mode is normal

B1L493 = B1L583 & B1L793 & !B1_count1_1[2] & !B1_count1_1[1];


--B1L301Q is rs422:inst|dsp0_data[15]~reg0
--operation mode is normal

B1L301Q_lut_out = dsp0_addr[3] & (B1L251 & (B1L451) # !B1L251 & B1L741) # !dsp0_addr[3] & (B1L251);
B1L301Q = DFFEAS(B1L301Q_lut_out, !dsp0_rd, VCC, , , , , , );


--B1L032Q is rs422:inst|p5~0
--operation mode is normal

B1L032Q_lut_out = !dsp0_addr[0] # !dsp0_addr[1] # !dsp0_addr[2] # !dsp0_addr[3];
B1L032Q = DFFEAS(B1L032Q_lut_out, !dsp0_rd, VCC, , , , , , );


--B1L201Q is rs422:inst|dsp0_data[14]~reg0
--operation mode is normal

B1L201Q_lut_out = dsp0_addr[0] & (B1L161 & (B1L361) # !B1L161 & B1L651) # !dsp0_addr[0] & (B1L161);
B1L201Q = DFFEAS(B1L201Q_lut_out, !dsp0_rd, VCC, , , , , , );


--B1L101Q is rs422:inst|dsp0_data[13]~reg0
--operation mode is normal

B1L101Q_lut_out = dsp0_addr[3] & (B1L071 & (B1L271) # !B1L071 & B1L561) # !dsp0_addr[3] & (B1L071);
B1L101Q = DFFEAS(B1L101Q_lut_out, !dsp0_rd, VCC, , , , , , );


--B1L001Q is rs422:inst|dsp0_data[12]~reg0
--operation mode is normal

B1L001Q_lut_out = dsp0_addr[0] & (B1L971 & (B1L181) # !B1L971 & B1L471) # !dsp0_addr[0] & (B1L971);
B1L001Q = DFFEAS(B1L001Q_lut_out, !dsp0_rd, VCC, , , , , , );


--B1L99Q is rs422:inst|dsp0_data[11]~reg0
--operation mode is normal

B1L99Q_lut_out = dsp0_addr[3] & (B1L881 & (B1L091) # !B1L881 & B1L381) # !dsp0_addr[3] & (B1L881);
B1L99Q = DFFEAS(B1L99Q_lut_out, !dsp0_rd, VCC, , , , , , );


--B1L89Q is rs422:inst|dsp0_data[10]~reg0
--operation mode is normal

B1L89Q_lut_out = dsp0_addr[0] & (B1L791 & (B1L991) # !B1L791 & B1L291) # !dsp0_addr[0] & (B1L791);
B1L89Q = DFFEAS(B1L89Q_lut_out, !dsp0_rd, VCC, , , , , , );


--B1L79Q is rs422:inst|dsp0_data[9]~reg0
--operation mode is normal

B1L79Q_lut_out = dsp0_addr[3] & (B1L602 & (B1L802) # !B1L602 & B1L102) # !dsp0_addr[3] & (B1L602);
B1L79Q = DFFEAS(B1L79Q_lut_out, !dsp0_rd, VCC, , , , , , );


--B1L69Q is rs422:inst|dsp0_data[8]~reg0
--operation mode is normal

B1L69Q_lut_out = dsp0_addr[0] & (B1L512 & (B1L712) # !B1L512 & B1L012) # !dsp0_addr[0] & (B1L512);
B1L69Q = DFFEAS(B1L69Q_lut_out, !dsp0_rd, VCC, , , , , , );


--B1L22 is rs422:inst|add~727
--operation mode is normal

B1L22_carry_eqn = B1L42;
B1L22 = B1_Dsum1[7] $ B1_Dout[7] $ B1L22_carry_eqn;


--A1L221 is rtl~667
--operation mode is normal

A1L221 = B1L322 & B1L822;


--A1L321 is rtl~668
--operation mode is normal

A1L321 = A1L911 & !B1L141 & (B1L931 # B1L041);


--B1L32 is rs422:inst|add~732
--operation mode is arithmetic

B1L32_carry_eqn = B1L62;
B1L32 = B1_Dsum1[6] $ B1_Dout[6] $ !B1L32_carry_eqn;

--B1L42 is rs422:inst|add~734
--operation mode is arithmetic

B1L42 = CARRY(B1_Dsum1[6] & (B1_Dout[6] # !B1L62) # !B1_Dsum1[6] & B1_Dout[6] & !B1L62);


--B1L52 is rs422:inst|add~737
--operation mode is arithmetic

B1L52_carry_eqn = B1L82;
B1L52 = B1_Dsum1[5] $ B1_Dout[5] $ B1L52_carry_eqn;

--B1L62 is rs422:inst|add~739
--operation mode is arithmetic

B1L62 = CARRY(B1_Dsum1[5] & !B1_Dout[5] & !B1L82 # !B1_Dsum1[5] & (!B1L82 # !B1_Dout[5]));


--B1L72 is rs422:inst|add~742
--operation mode is arithmetic

B1L72_carry_eqn = B1L03;
B1L72 = B1_Dsum1[4] $ B1_Dout[4] $ !B1L72_carry_eqn;

--B1L82 is rs422:inst|add~744
--operation mode is arithmetic

B1L82 = CARRY(B1_Dsum1[4] & (B1_Dout[4] # !B1L03) # !B1_Dsum1[4] & B1_Dout[4] & !B1L03);


--B1L92 is rs422:inst|add~747
--operation mode is arithmetic

B1L92_carry_eqn = B1L23;
B1L92 = B1_Dsum1[3] $ B1_Dout[3] $ B1L92_carry_eqn;

--B1L03 is rs422:inst|add~749
--operation mode is arithmetic

B1L03 = CARRY(B1_Dsum1[3] & !B1_Dout[3] & !B1L23 # !B1_Dsum1[3] & (!B1L23 # !B1_Dout[3]));


--B1L13 is rs422:inst|add~752
--operation mode is arithmetic

B1L13_carry_eqn = B1L43;
B1L13 = B1_Dsum1[2] $ B1_Dout[2] $ !B1L13_carry_eqn;

--B1L23 is rs422:inst|add~754
--operation mode is arithmetic

B1L23 = CARRY(B1_Dsum1[2] & (B1_Dout[2] # !B1L43) # !B1_Dsum1[2] & B1_Dout[2] & !B1L43);


--B1L33 is rs422:inst|add~757
--operation mode is arithmetic

B1L33_carry_eqn = B1L6;
B1L33 = B1_Dsum1[1] $ B1_Dout[1] $ B1L33_carry_eqn;

--B1L43 is rs422:inst|add~759
--operation mode is arithmetic

B1L43 = CARRY(B1_Dsum1[1] & !B1_Dout[1] & !B1L6 # !B1_Dsum1[1] & (!B1L6 # !B1_Dout[1]));


--A1L011 is rtl~28
--operation mode is normal

A1L011 = B1L722 & !B1L922 & (B1_Dout[3] $ B1_Dout[2]);


--A1L111 is rtl~29
--operation mode is normal

A1L111 = B1L141 # !B1L324 # !A1L021;


--B1L621 is rs422:inst|LENGTH1_1~120
--operation mode is normal

B1L621 = B1L324 & (A1L021 & B1_LENGTH1_1[0] # !A1L021 & (!B1L811));


--B1L331 is rs422:inst|LENGTH1_2~352
--operation mode is normal

B1L331 = B1L922 & B1_LENGTH1_2[2] # !B1L922 & (B1L722 & (!B1_Dout[2]) # !B1L722 & B1_LENGTH1_2[2]);


--B1L431 is rs422:inst|LENGTH1_2~354
--operation mode is normal

B1L431 = B1L722 & (B1L922 & B1_LENGTH1_2[1] # !B1L922 & (B1_Dout[1])) # !B1L722 & B1_LENGTH1_2[1];


--B1L531 is rs422:inst|LENGTH1_2~356
--operation mode is normal

B1L531 = B1L722 & (B1L922 & B1_LENGTH1_2[0] # !B1L922 & (B1_Dout[0])) # !B1L722 & B1_LENGTH1_2[0];


--B1L07 is rs422:inst|Decoder~187
--operation mode is normal

B1L07 = !B1_WP[0] & B1_WP[1] & !B1_WP[2] & !B1_WP[3];


--B1L062 is rs422:inst|RAM1[2][7]~1305
--operation mode is normal

B1L062 = B1L76 & B1L07;


--B1L17 is rs422:inst|Decoder~188
--operation mode is normal

B1L17 = B1_WP[0] & B1_WP[1] & !B1_WP[2] & !B1_WP[3];


--B1L072 is rs422:inst|RAM1[3][7]~1306
--operation mode is normal

B1L072 = B1L76 & B1L17;


--D1_clk_19_2k is clk:inst12|clk_19_2k
--operation mode is normal

D1_clk_19_2k_lut_out = D1_count1[10] # D1_count1[9] & (D1_count1[8] # !D1L001);
D1_clk_19_2k = DFFEAS(D1_clk_19_2k_lut_out, !G1__clk0, VCC, , , , , , );


--D1L19 is clk:inst12|LessThan~1225
--operation mode is normal

D1L19 = D1_count3[5] & D1_count3[4] & D1_count3[3] & D1_count3[2];


--D1_tag0 is clk:inst12|tag0
--operation mode is normal

D1_tag0_lut_out = !D1L19 & D1_tag0 # !D1_CLK200K;
D1_tag0 = DFFEAS(D1_tag0_lut_out, !D1_clk_19_2k, VCC, , , , , , );


--A1L211 is rtl~32
--operation mode is normal

A1L211 = D1_tag0 # !D1_CLK200K;


--A1L311 is rtl~33
--operation mode is normal

A1L311 = B1L822 & (!B1L322);


--B1L441 is rs422:inst|LessThan~689
--operation mode is normal

B1L441 = B1_WP[2] & B1_WP[1] & B1_WP[0];


--B1L541 is rs422:inst|LessThan~690
--operation mode is normal

B1L541 = B1_WP[1] & B1_WP[0];


--D1L29 is clk:inst12|LessThan~1226
--operation mode is normal

D1L29 = D1_count0[5] & D1_count0[4] & (D1_count0[3] # !D1L11);


--B1L911 is rs422:inst|flag~306
--operation mode is normal

B1L911 = B1L483 & B1L583 & !B1_count1_1[1] & !RXD;


--F1_q_a[1] is rs422:inst|altsyncram:reduce_nor_rtl_0|altsyncram_h0j:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 3
--Port A Input: Registered, Port A Output: Un-registered
F1_q_a[1]_PORT_A_address = BUS(B1L74, B1L94, B1L05, B1L25, B1L45, B1L65, B1L75, B1L54);
F1_q_a[1]_PORT_A_address_reg = DFFE(F1_q_a[1]_PORT_A_address, F1_q_a[1]_clock_0, , , );
F1_q_a[1]_clock_0 = D1_CLK_SERIAL;
F1_q_a[1]_PORT_A_data_out = MEMORY(, , F1_q_a[1]_PORT_A_address_reg, , , , , , F1_q_a[1]_clock_0, , , , , );
F1_q_a[1] = F1_q_a[1]_PORT_A_data_out[0];


--B1L59 is rs422:inst|Dout[7]~177
--operation mode is normal

B1L59 = RXD & B1_count1_1[0] & (!B1_count1_1[1]);


--B1L021 is rs422:inst|flag~307
--operation mode is normal

B1L021 = F1_q_a[1] # B1L283 & B1L683 & B1L59;


--D1L39 is clk:inst12|LessThan~1227
--operation mode is normal

D1L39 = !D1_count2[8] & !D1_count2[9] # !D1_count2[11] # !D1_count2[10];


--D1_count2[0] is clk:inst12|count2[0]
--operation mode is arithmetic

D1_count2[0]_lut_out = !D1_count2[0];
D1_count2[0] = DFFEAS(D1_count2[0]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L14 is clk:inst12|count2[0]~340
--operation mode is arithmetic

D1L14 = CARRY(D1_count2[0]);


--D1L49 is clk:inst12|LessThan~1228
--operation mode is normal

D1L49 = !D1_count2[0] # !D1_count2[5] # !D1_count2[4] # !D1_count2[3];


--D1_count2[1] is clk:inst12|count2[1]
--operation mode is arithmetic

D1_count2[1]_carry_eqn = D1L14;
D1_count2[1]_lut_out = D1_count2[1] $ (D1_count2[1]_carry_eqn);
D1_count2[1] = DFFEAS(D1_count2[1]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L34 is clk:inst12|count2[1]~344
--operation mode is arithmetic

D1L34 = CARRY(!D1L14 # !D1_count2[1]);


--D1_count2[2] is clk:inst12|count2[2]
--operation mode is arithmetic

D1_count2[2]_carry_eqn = D1L34;
D1_count2[2]_lut_out = D1_count2[2] $ (!D1_count2[2]_carry_eqn);
D1_count2[2] = DFFEAS(D1_count2[2]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L54 is clk:inst12|count2[2]~348
--operation mode is arithmetic

D1L54 = CARRY(D1_count2[2] & (!D1L34));


--D1L59 is clk:inst12|LessThan~1229
--operation mode is normal

D1L59 = D1_count2[6] # !D1L49 & D1_count2[1] & D1_count2[2];


--D1L69 is clk:inst12|LessThan~1230
--operation mode is normal

D1L69 = !D1L39 & (D1_count2[7] # D1_count2[9] # D1L59);


--D1L79 is clk:inst12|LessThan~1231
--operation mode is normal

D1L79 = D1_count2[16] & D1_count2[17] & (D1L69 # !D1L78);


--B1L49 is rs422:inst|Dout[7]~0
--operation mode is normal

B1L49 = B1L283 & B1L783 & B1L683 & B1L59;


--B1_RAM1[10][7] is rs422:inst|RAM1[10][7]
--operation mode is normal

B1_RAM1[10][7]_lut_out = B1_Dout[7];
B1_RAM1[10][7] = DFFEAS(B1_RAM1[10][7]_lut_out, !B1_D_enp, VCC, , B1L043, , , , );


--B1_RAM1[9][7] is rs422:inst|RAM1[9][7]
--operation mode is normal

B1_RAM1[9][7]_lut_out = B1_Dout[7];
B1_RAM1[9][7] = DFFEAS(B1_RAM1[9][7]_lut_out, !B1_D_enp, VCC, , B1L033, , , , );


--B1_RAM1[8][7] is rs422:inst|RAM1[8][7]
--operation mode is normal

B1_RAM1[8][7]_lut_out = B1_Dout[7];
B1_RAM1[8][7] = DFFEAS(B1_RAM1[8][7]_lut_out, !B1_D_enp, VCC, , B1L023, , , , );


--B1L641 is rs422:inst|Mux~1067
--operation mode is normal

B1L641 = dsp0_addr[1] & (dsp0_addr[0]) # !dsp0_addr[1] & (dsp0_addr[0] & B1_RAM1[9][7] # !dsp0_addr[0] & (B1_RAM1[8][7]));


--B1_RAM1[11][7] is rs422:inst|RAM1[11][7]
--operation mode is normal

B1_RAM1[11][7]_lut_out = B1_Dout[7];
B1_RAM1[11][7] = DFFEAS(B1_RAM1[11][7]_lut_out, !B1_D_enp, VCC, , B1L053, , , , );


--B1L741 is rs422:inst|Mux~1068
--operation mode is normal

B1L741 = dsp0_addr[1] & (B1L641 & (B1_RAM1[11][7]) # !B1L641 & B1_RAM1[10][7]) # !dsp0_addr[1] & (B1L641);


--B1_RAM1[5][7] is rs422:inst|RAM1[5][7]
--operation mode is normal

B1_RAM1[5][7]_lut_out = B1_Dout[7];
B1_RAM1[5][7] = DFFEAS(B1_RAM1[5][7]_lut_out, !B1_D_enp, VCC, , B1L092, , , , );


--B1_RAM1[6][7] is rs422:inst|RAM1[6][7]
--operation mode is normal

B1_RAM1[6][7]_lut_out = B1_Dout[7];
B1_RAM1[6][7] = DFFEAS(B1_RAM1[6][7]_lut_out, !B1_D_enp, VCC, , B1L003, , , , );


--B1_RAM1[4][7] is rs422:inst|RAM1[4][7]
--operation mode is normal

B1_RAM1[4][7]_lut_out = B1_Dout[7];
B1_RAM1[4][7] = DFFEAS(B1_RAM1[4][7]_lut_out, !B1_D_enp, VCC, , B1L082, , , , );


--B1L841 is rs422:inst|Mux~1069
--operation mode is normal

B1L841 = dsp0_addr[0] & (dsp0_addr[1]) # !dsp0_addr[0] & (dsp0_addr[1] & B1_RAM1[6][7] # !dsp0_addr[1] & (B1_RAM1[4][7]));


--B1_RAM1[7][7] is rs422:inst|RAM1[7][7]