test.map.eqn

FPGA串口界面调试程序,用VHDL语言实现

--operation mode is arithmetic

D1L97 = CARRY(!D1L77 # !D1_count3[1]);


--D1_count3[0] is clk:inst12|count3[0]
--operation mode is arithmetic

D1_count3[0]_lut_out = !D1_count3[0];
D1_count3[0] = DFFEAS(D1_count3[0]_lut_out, !D1_clk_19_2k, VCC, , A1L211, ~GND, , !D1_CLK200K, D1L19);

--D1L77 is clk:inst12|count3[0]~115
--operation mode is arithmetic

D1L77 = CARRY(D1_count3[0]);


--B1_STATE_1[1] is rs422:inst|STATE_1[1]
--operation mode is normal

B1_STATE_1[1]_lut_out = A1L111 & (B1L812 $ !A1L311) # !A1L111 & (B1_STATE_1[1]);
B1_STATE_1[1] = DFFEAS(B1_STATE_1[1]_lut_out, !B1_D_enp, VCC, , , , , , );


--B1_STATE_1[0] is rs422:inst|STATE_1[0]
--operation mode is normal

B1_STATE_1[0]_lut_out = A1L111 & (B1L822 $ B1L812) # !A1L111 & B1_STATE_1[0];
B1_STATE_1[0] = DFFEAS(B1_STATE_1[0]_lut_out, !B1_D_enp, VCC, , , , , , );


--B1_WP[3] is rs422:inst|WP[3]
--operation mode is normal

B1_WP[3]_lut_out = A1L021 & (B1_WP[3] $ B1L441) # !A1L021 & !B1L324 & (B1_WP[3] $ B1L441);
B1_WP[3] = DFFEAS(B1_WP[3]_lut_out, !B1_D_enp, VCC, , , , , , );


--B1_WP[2] is rs422:inst|WP[2]
--operation mode is normal

B1_WP[2]_lut_out = A1L321 & (B1_WP[2] $ B1L541) # !A1L321 & !B1L324 & (B1_WP[2] $ B1L541);
B1_WP[2] = DFFEAS(B1_WP[2]_lut_out, !B1_D_enp, VCC, , , , , , );


--B1_WP[1] is rs422:inst|WP[1]
--operation mode is normal

B1_WP[1]_lut_out = A1L321 & (B1_WP[1] $ B1_WP[0]) # !A1L321 & !B1L324 & (B1_WP[1] $ B1_WP[0]);
B1_WP[1] = DFFEAS(B1_WP[1]_lut_out, !B1_D_enp, VCC, , , , , , );


--B1_WP[0] is rs422:inst|WP[0]
--operation mode is normal

B1_WP[0]_lut_out = !B1_WP[0] & (A1L321 # !B1L324);
B1_WP[0] = DFFEAS(B1_WP[0]_lut_out, !B1_D_enp, VCC, , , , , , );


--B1L96 is rs422:inst|D_valid1_2~8
--operation mode is normal

B1L96 = !B1_D_valid1_1p & (!B1_count1_2[1] # !B1_count1_2[2] # !B1_count1_2[3]);


--D1_count0[5] is clk:inst12|count0[5]
--operation mode is normal

D1_count0[5]_carry_eqn = D1L51;
D1_count0[5]_lut_out = D1_count0[5] $ (D1_count0[5]_carry_eqn);
D1_count0[5] = DFFEAS(D1_count0[5]_lut_out, G1__clk0, VCC, , , , , D1L29, );


--D1_count0[4] is clk:inst12|count0[4]
--operation mode is arithmetic

D1_count0[4]_carry_eqn = D1L31;
D1_count0[4]_lut_out = D1_count0[4] $ (!D1_count0[4]_carry_eqn);
D1_count0[4] = DFFEAS(D1_count0[4]_lut_out, G1__clk0, VCC, , , , , D1L29, );

--D1L51 is clk:inst12|count0[4]~131
--operation mode is arithmetic

D1L51 = CARRY(D1_count0[4] & (!D1L31));


--D1_count0[3] is clk:inst12|count0[3]
--operation mode is arithmetic

D1_count0[3]_carry_eqn = D1L01;
D1_count0[3]_lut_out = D1_count0[3] $ (D1_count0[3]_carry_eqn);
D1_count0[3] = DFFEAS(D1_count0[3]_lut_out, G1__clk0, VCC, , , , , D1L29, );

--D1L31 is clk:inst12|count0[3]~135
--operation mode is arithmetic

D1L31 = CARRY(!D1L01 # !D1_count0[3]);


--D1_count0[0] is clk:inst12|count0[0]
--operation mode is arithmetic

D1_count0[0]_lut_out = !D1_count0[0];
D1_count0[0] = DFFEAS(D1_count0[0]_lut_out, G1__clk0, VCC, , , , , D1L29, );

--D1L6 is clk:inst12|count0[0]~139
--operation mode is arithmetic

D1L6 = CARRY(D1_count0[0]);


--D1_count0[1] is clk:inst12|count0[1]
--operation mode is arithmetic

D1_count0[1]_carry_eqn = D1L6;
D1_count0[1]_lut_out = D1_count0[1] $ (D1_count0[1]_carry_eqn);
D1_count0[1] = DFFEAS(D1_count0[1]_lut_out, G1__clk0, VCC, , , , , D1L29, );

--D1L8 is clk:inst12|count0[1]~143
--operation mode is arithmetic

D1L8 = CARRY(!D1L6 # !D1_count0[1]);


--D1_count0[2] is clk:inst12|count0[2]
--operation mode is arithmetic

D1_count0[2]_carry_eqn = D1L8;
D1_count0[2]_lut_out = D1_count0[2] $ (!D1_count0[2]_carry_eqn);
D1_count0[2] = DFFEAS(D1_count0[2]_lut_out, G1__clk0, VCC, , , , , D1L29, );

--D1L01 is clk:inst12|count0[2]~147
--operation mode is arithmetic

D1L01 = CARRY(D1_count0[2] & (!D1L8));


--D1L11 is clk:inst12|count0[2]~150
--operation mode is normal

D1L11 = !D1_count0[0] & !D1_count0[1] & !D1_count0[2];


--G1__clk0 is PLL24M:inst7|altpll:altpll_component|_clk0
G1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(CLK40M), .INCLK(), .CLKENA(), .CLKENA(GND), .CLKENA(GND), .CLKENA(GND), .CLKENA(GND), .CLKENA(GND), .EXTCLKENA(GND), .EXTCLKENA(GND), .EXTCLKENA(GND), .EXTCLKENA(GND));


--B1_\p1:flag[0] is rs422:inst|\p1:flag[0]
--operation mode is normal

B1_\p1:flag[0]_lut_out = B1_\p1:flag[0] & (B1_\p1:flag[1] # !B1L183) # !B1_\p1:flag[0] & !B1_\p1:flag[1] & !RXD;
B1_\p1:flag[0] = DFFEAS(B1_\p1:flag[0]_lut_out, D1_CLK_SERIAL, VCC, , , , , , );


--F1_q_a[2] is rs422:inst|altsyncram:reduce_nor_rtl_0|altsyncram_h0j:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 3
--Port A Input: Registered, Port A Output: Un-registered
F1_q_a[2]_PORT_A_address = BUS(B1L74, B1L94, B1L05, B1L25, B1L45, B1L65, B1L75, B1L54);
F1_q_a[2]_PORT_A_address_reg = DFFE(F1_q_a[2]_PORT_A_address, F1_q_a[2]_clock_0, , , );
F1_q_a[2]_clock_0 = D1_CLK_SERIAL;
F1_q_a[2]_PORT_A_data_out = MEMORY(, , F1_q_a[2]_PORT_A_address_reg, , , , , , F1_q_a[2]_clock_0, , , , , );
F1_q_a[2] = F1_q_a[2]_PORT_A_data_out[0];


--A1L411 is rtl~656
--operation mode is normal

A1L411 = B1_\p1:flag[0] # B1_D_enp & F1_q_a[2];


--B1L283 is rs422:inst|reduce_nor~206
--operation mode is normal

B1L283 = B1_count1_1[7] & B1_count1_1[6] & !B1_count1_1[4] & !B1_count1_1[2];


--B1L383 is rs422:inst|reduce_nor~207
--operation mode is normal

B1L383 = B1_count1_1[5] & B1_count1_1[3] & B1_count1_1[1] & B1_count1_1[0];


--B1_\p1:flag[1] is rs422:inst|\p1:flag[1]
--operation mode is normal

B1_\p1:flag[1]_lut_out = B1_\p1:flag[0] & (B1_\p1:flag[1] # B1L911) # !B1_\p1:flag[0] & B1_\p1:flag[1] & (B1L021);
B1_\p1:flag[1] = DFFEAS(B1_\p1:flag[1]_lut_out, D1_CLK_SERIAL, VCC, , , , , , );


--F1_q_a[0] is rs422:inst|altsyncram:reduce_nor_rtl_0|altsyncram_h0j:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 3
--Port A Input: Registered, Port A Output: Un-registered
F1_q_a[0]_PORT_A_address = BUS(B1L74, B1L94, B1L05, B1L25, B1L45, B1L65, B1L75, B1L54);
F1_q_a[0]_PORT_A_address_reg = DFFE(F1_q_a[0]_PORT_A_address, F1_q_a[0]_clock_0, , , );
F1_q_a[0]_clock_0 = D1_CLK_SERIAL;
F1_q_a[0]_PORT_A_data_out = MEMORY(, , F1_q_a[0]_PORT_A_address_reg, , , , , , F1_q_a[0]_clock_0, , , , , );
F1_q_a[0] = F1_q_a[0]_PORT_A_data_out[0];


--A1L511 is rtl~657
--operation mode is normal

A1L511 = !F1_q_a[0] & (RXD # B1_\p1:flag[1]);


--B1L483 is rs422:inst|reduce_nor~208
--operation mode is normal

B1L483 = B1_count1_1[2] & (!B1_count1_1[6] & !B1_count1_1[4]);


--B1L583 is rs422:inst|reduce_nor~209
--operation mode is normal

B1L583 = B1_count1_1[3] & B1_count1_1[0] & !B1_count1_1[7] & !B1_count1_1[5];


--B1L183 is rs422:inst|reduce_nor~2
--operation mode is normal

B1L183 = B1L483 & B1L583 & (!B1_count1_1[1]);


--A1L611 is rtl~658
--operation mode is normal

A1L611 = B1_\p1:flag[1] & (!B1_\p1:flag[0]) # !B1_\p1:flag[1] & (B1_\p1:flag[0] & B1L183 # !B1_\p1:flag[0] & (!RXD));


--B1L683 is rs422:inst|reduce_nor~210
--operation mode is normal

B1L683 = B1_count1_1[5] & (!B1_count1_1[3]);


--A1L711 is rtl~659
--operation mode is normal

A1L711 = B1L383 # B1_count1_1[1] & !B1_count1_1[0] & B1L683;


--A1L811 is rtl~660
--operation mode is normal

A1L811 = B1_D_busyp # B1L283 & A1L711 # !A1L511;


--D1_count2[12] is clk:inst12|count2[12]
--operation mode is arithmetic

D1_count2[12]_carry_eqn = D1L36;
D1_count2[12]_lut_out = D1_count2[12] $ (!D1_count2[12]_carry_eqn);
D1_count2[12] = DFFEAS(D1_count2[12]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L56 is clk:inst12|count2[12]~280
--operation mode is arithmetic

D1L56 = CARRY(D1_count2[12] & (!D1L36));


--D1_count2[13] is clk:inst12|count2[13]
--operation mode is arithmetic

D1_count2[13]_carry_eqn = D1L56;
D1_count2[13]_lut_out = D1_count2[13] $ (D1_count2[13]_carry_eqn);
D1_count2[13] = DFFEAS(D1_count2[13]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L76 is clk:inst12|count2[13]~284
--operation mode is arithmetic

D1L76 = CARRY(!D1L56 # !D1_count2[13]);


--D1_count2[14] is clk:inst12|count2[14]
--operation mode is arithmetic

D1_count2[14]_carry_eqn = D1L76;
D1_count2[14]_lut_out = D1_count2[14] $ (!D1_count2[14]_carry_eqn);
D1_count2[14] = DFFEAS(D1_count2[14]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L96 is clk:inst12|count2[14]~288
--operation mode is arithmetic

D1L96 = CARRY(D1_count2[14] & (!D1L76));


--D1_count2[15] is clk:inst12|count2[15]
--operation mode is arithmetic

D1_count2[15]_carry_eqn = D1L96;
D1_count2[15]_lut_out = D1_count2[15] $ (D1_count2[15]_carry_eqn);
D1_count2[15] = DFFEAS(D1_count2[15]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L17 is clk:inst12|count2[15]~292
--operation mode is arithmetic

D1L17 = CARRY(!D1L96 # !D1_count2[15]);


--D1L78 is clk:inst12|LessThan~1220
--operation mode is normal

D1L78 = !D1_count2[12] & !D1_count2[13] & !D1_count2[14] & !D1_count2[15];


--D1_count2[8] is clk:inst12|count2[8]
--operation mode is arithmetic

D1_count2[8]_carry_eqn = D1L55;
D1_count2[8]_lut_out = D1_count2[8] $ (!D1_count2[8]_carry_eqn);
D1_count2[8] = DFFEAS(D1_count2[8]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L75 is clk:inst12|count2[8]~296
--operation mode is arithmetic

D1L75 = CARRY(D1_count2[8] & (!D1L55));


--D1_count2[9] is clk:inst12|count2[9]
--operation mode is arithmetic

D1_count2[9]_carry_eqn = D1L75;
D1_count2[9]_lut_out = D1_count2[9] $ (D1_count2[9]_carry_eqn);
D1_count2[9] = DFFEAS(D1_count2[9]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L95 is clk:inst12|count2[9]~300
--operation mode is arithmetic

D1L95 = CARRY(!D1L75 # !D1_count2[9]);


--D1_count2[10] is clk:inst12|count2[10]
--operation mode is arithmetic

D1_count2[10]_carry_eqn = D1L95;
D1_count2[10]_lut_out = D1_count2[10] $ (!D1_count2[10]_carry_eqn);
D1_count2[10] = DFFEAS(D1_count2[10]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L16 is clk:inst12|count2[10]~304
--operation mode is arithmetic

D1L16 = CARRY(D1_count2[10] & (!D1L95));


--D1_count2[11] is clk:inst12|count2[11]
--operation mode is arithmetic

D1_count2[11]_carry_eqn = D1L16;
D1_count2[11]_lut_out = D1_count2[11] $ (D1_count2[11]_carry_eqn);
D1_count2[11] = DFFEAS(D1_count2[11]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L36 is clk:inst12|count2[11]~308
--operation mode is arithmetic

D1L36 = CARRY(!D1L16 # !D1_count2[11]);


--D1L88 is clk:inst12|LessThan~1221
--operation mode is normal

D1L88 = !D1_count2[8] & !D1_count2[9] & !D1_count2[10] & !D1_count2[11];


--D1_count2[3] is clk:inst12|count2[3]
--operation mode is arithmetic

D1_count2[3]_carry_eqn = D1L54;
D1_count2[3]_lut_out = D1_count2[3] $ (D1_count2[3]_carry_eqn);
D1_count2[3] = DFFEAS(D1_count2[3]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L74 is clk:inst12|count2[3]~312
--operation mode is arithmetic

D1L74 = CARRY(!D1L54 # !D1_count2[3]);


--D1_count2[4] is clk:inst12|count2[4]
--operation mode is arithmetic

D1_count2[4]_carry_eqn = D1L74;
D1_count2[4]_lut_out = D1_count2[4] $ (!D1_count2[4]_carry_eqn);
D1_count2[4] = DFFEAS(D1_count2[4]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L94 is clk:inst12|count2[4]~316
--operation mode is arithmetic

D1L94 = CARRY(D1_count2[4] & (!D1L74));


--D1_count2[5] is clk:inst12|count2[5]
--operation mode is arithmetic

D1_count2[5]_carry_eqn = D1L94;
D1_count2[5]_lut_out = D1_count2[5] $ (D1_count2[5]_carry_eqn);
D1_count2[5] = DFFEAS(D1_count2[5]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L15 is clk:inst12|count2[5]~320
--operation mode is arithmetic

D1L15 = CARRY(!D1L94 # !D1_count2[5]);


--D1_count2[6] is clk:inst12|count2[6]
--operation mode is arithmetic

D1_count2[6]_carry_eqn = D1L15;
D1_count2[6]_lut_out = D1_count2[6] $ (!D1_count2[6]_carry_eqn);
D1_count2[6] = DFFEAS(D1_count2[6]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L35 is clk:inst12|count2[6]~324
--operation mode is arithmetic

D1L35 = CARRY(D1_count2[6] & (!D1L15));


--D1L98 is clk:inst12|LessThan~1222
--operation mode is normal

D1L98 = !D1_count2[3] & !D1_count2[4] & !D1_count2[5] # !D1_count2[6];


--D1_count2[7] is clk:inst12|count2[7]
--operation mode is arithmetic

D1_count2[7]_carry_eqn = D1L35;
D1_count2[7]_lut_out = D1_count2[7] $ (D1_count2[7]_carry_eqn);
D1_count2[7] = DFFEAS(D1_count2[7]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L55 is clk:inst12|count2[7]~328
--operation mode is arithmetic

D1L55 = CARRY(!D1L35 # !D1_count2[7]);


--D1L09 is clk:inst12|LessThan~1223
--operation mode is normal

D1L09 = D1L78 & D1L88 & (D1L98 # !D1_count2[7]);


--D1_count2[16] is clk:inst12|count2[16]
--operation mode is arithmetic

D1_count2[16]_carry_eqn = D1L17;
D1_count2[16]_lut_out = D1_count2[16] $ (!D1_count2[16]_carry_eqn);
D1_count2[16] = DFFEAS(D1_count2[16]_lut_out, CLK40M, VCC, , , , , D1L79, );

--D1L37 is clk:inst12|count2[16]~332
--operation mode is arithmetic

D1L37 = CARRY(D1_count2[16] & (!D1L17));


--D1_count2[17] is clk:inst12|count2[17]
--operation mode is normal

D1_count2[17]_carry_eqn = D1L37;
D1_count2[17]_lut_out = D1_count2[17] $ (D1_count2[17]_carry_eqn);
D1_count2[17] = DFFEAS(D1_count2[17]_lut_out, CLK40M, VCC, , , , , D1L79, );


--A1L911 is rtl~661
--operation mode is normal

A1L911 = B1_LENGTH1_1[3] # B1_LENGTH1_1[2] # B1_LENGTH1_1[1] # B1_LENGTH1_1[0];


--B1L731 is rs422:inst|LessThan~682
--operation mode is normal

B1L731 = B1_LENGTH1_1[1] & !B1_WP[1] & (B1_LENGTH1_1[0] # !B1_WP[0]) # !B1_LENGTH1_1[1] & !B1_LENGTH1_1[0] & (!B1_WP[1] # !B1_WP[0]);


--B1L831 is rs422:inst|LessThan~683
--operation mode is normal

B1L831 = B1_LENGTH1_1[2] $ B1_WP[2] $ (B1_LENGTH1_1[1] # B1_LENGTH1_1[0]);