test.qsf

FPGA串口界面调试程序,用VHDL语言实现

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		test_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:29:59  JULY 20, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VHDL_FILE test.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE test.vwf
set_global_assignment -name BDF_FILE test.bdf
set_global_assignment -name MIF_FILE chuankourom.mif

# Pin & Location Assignments
# ==========================
set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
set_location_assignment PIN_U22 -to dsp0_irq
set_location_assignment PIN_M22 -to dsp0_rd
set_location_assignment PIN_K22 -to dsp0_addr[0]
set_location_assignment PIN_K21 -to dsp0_addr[1]
set_location_assignment PIN_K20 -to dsp0_addr[2]
set_location_assignment PIN_K19 -to dsp0_addr[3]
set_location_assignment PIN_A9 -to dsp0_data[8]
set_location_assignment PIN_H16 -to dsp0_data[9]
set_location_assignment PIN_C15 -to dsp0_data[10]
set_location_assignment PIN_C9 -to dsp0_data[11]
set_location_assignment PIN_D17 -to dsp0_data[12]
set_location_assignment PIN_F15 -to dsp0_data[13]
set_location_assignment PIN_A10 -to dsp0_data[14]
set_location_assignment PIN_C17 -to dsp0_data[15]
set_location_assignment PIN_K1 -to irq0
set_location_assignment PIN_P6 -to dsp0rd
set_location_assignment PIN_AD7 -to rdtest
set_location_assignment PIN_AC4 -to ramtest1[7]
set_location_assignment PIN_AD4 -to ramtest1[6]
set_location_assignment PIN_R5 -to ramtest1[5]
set_location_assignment PIN_R4 -to ramtest1[4]
set_location_assignment PIN_T4 -to ramtest1[3]
set_location_assignment PIN_T5 -to ramtest1[2]
set_location_assignment PIN_U3 -to ramtest1[1]
set_location_assignment PIN_U4 -to ramtest1[0]
set_location_assignment PIN_V5 -to ramtest2[7]
set_location_assignment PIN_V6 -to ramtest2[6]
set_location_assignment PIN_W9 -to ramtest2[5]
set_location_assignment PIN_W10 -to ramtest2[4]
set_location_assignment PIN_Y3 -to ramtest2[3]
set_location_assignment PIN_Y4 -to ramtest2[2]
set_location_assignment PIN_AA3 -to ramtest2[1]
set_location_assignment PIN_AA4 -to ramtest2[0]
set_location_assignment PIN_AB3 -to dsp0datatest[15]
set_location_assignment PIN_AB4 -to dsp0datatest[14]
set_location_assignment PIN_AF9 -to dsp0datatest[13]
set_location_assignment PIN_AE8 -to dsp0datatest[12]
set_location_assignment PIN_AF8 -to dsp0datatest[11]
set_location_assignment PIN_AE7 -to dsp0datatest[10]
set_location_assignment PIN_AF7 -to dsp0datatest[9]
set_location_assignment PIN_AE6 -to dsp0datatest[8]
set_location_assignment PIN_AF6 -to addrtest[3]
set_location_assignment PIN_AE4 -to addrtest[2]
set_location_assignment PIN_AE3 -to addrtest[1]
set_location_assignment PIN_AE2 -to addrtest[0]
set_location_assignment PIN_R6 -to rdtestD
set_location_assignment PIN_A15 -to CLK40M
set_location_assignment PIN_M6 -to RXD
set_location_assignment PIN_AA1 -to RXDOUT

# Timing Assignments
# ==================
set_global_assignment -name DO_MIN_ANALYSIS ON
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY Stratix
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name TOP_LEVEL_ENTITY test

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1S20F672I7
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name OPTIMIZE_TIMING NORMAL_COMPILATION
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX NORMAL
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# Timing Analysis Assignments
# ===========================
set_global_assignment -name MAX_SCC_SIZE 50

# Assembler Assignments
# =====================
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPC8
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF

# Design Assistant Assignments
# ============================
set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
set_global_assignment -name ASSG_CAT OFF
set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
set_global_assignment -name SIGNALRACE_RULE_TRISTATE OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
set_global_assignment -name CLK_CAT OFF
set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
set_global_assignment -name CLK_RULE_INV_CLOCK OFF
set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
set_global_assignment -name CLK_RULE_MIX_EDGES OFF
set_global_assignment -name RESET_CAT OFF
set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
set_global_assignment -name TIMING_CAT OFF
set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
set_global_assignment -name SIGNALRACE_CAT OFF
set_global_assignment -name ACLK_CAT OFF
set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
set_global_assignment -name HCPY_CAT OFF
set_global_assignment -name HCPY_VREF_PINS OFF

# SignalTap II Assignments
# ========================
set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST