test.map.qmsg

FPGA串口界面调试程序,用VHDL语言实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 09 16:09:29 2006 " "Info: Processing started: Wed Aug 09 16:09:29 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off test -c test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test" {  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.vhd " "Warning: Can't analyze file -- file C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.vhd is missing" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 test " "Info: Found entity 1: test" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "test " "Info: Elaborating entity \"test\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "tapg1p\[1..0\] " "Warning: Pin \"tapg1p\[1..0\]\" is missing source" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.bdf" { { 200 1160 1349 216 "tapg1p\[1..0\]" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "rs422.vhd 2 1 " "Info: Using design file rs422.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rs422-rtl " "Info: Found design unit 1: rs422-rtl" {  } { { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 38 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 rs422 " "Info: Found entity 1: rs422" {  } { { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rs422 rs422:inst " "Info: Elaborating entity \"rs422\" for hierarchy \"rs422:inst\"" {  } { { "test.bdf" "inst" { Schematic "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.bdf" { { -160 560 784 256 "inst" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "count1_3 rs422.vhd(56) " "Info: (10035) Verilog HDL or VHDL information at rs422.vhd(56): object \"count1_3\" declared but not used" {  } { { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 56 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "RAM2 rs422.vhd(61) " "Info: (10035) Verilog HDL or VHDL information at rs422.vhd(61): object \"RAM2\" declared but not used" {  } { { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 61 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "clk.vhd 2 1 " "Info: Using design file clk.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clk-rtl " "Info: Found design unit 1: clk-rtl" {  } { { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 clk " "Info: Found entity 1: clk" {  } { { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk clk:inst12 " "Info: Elaborating entity \"clk\" for hierarchy \"clk:inst12\"" {  } { { "test.bdf" "inst12" { Schematic "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.bdf" { { 80 80 256 240 "inst12" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "clk_16m clk.vhd(22) " "Info: (10035) Verilog HDL or VHDL information at clk.vhd(22): object \"clk_16m\" declared but not used" {  } { { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 22 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "clk_8m clk.vhd(22) " "Info: (10035) Verilog HDL or VHDL information at clk.vhd(22): object \"clk_8m\" declared but not used" {  } { { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 22 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "PLL24M.vhd 2 1 " "Info: Using design file PLL24M.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PLL24M-SYN " "Info: Found design unit 1: PLL24M-SYN" {  } { { "PLL24M.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/PLL24M.vhd" 48 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 PLL24M " "Info: Found entity 1: PLL24M" {  } { { "PLL24M.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/PLL24M.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL24M PLL24M:inst7 " "Info: Elaborating entity \"PLL24M\" for hierarchy \"PLL24M:inst7\"" {  } { { "test.bdf" "inst7" { Schematic "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.bdf" { { -168 64 304 -8 "inst7" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll PLL24M:inst7\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"PLL24M:inst7\|altpll:altpll_component\"" {  } { { "PLL24M.vhd" "altpll_component" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/PLL24M.vhd" 98 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "rs422:inst\|tag1 High " "Info: Power-up level of register \"rs422:inst\|tag1\" is not specified -- using power-up level of High to minimize register" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rs422:inst\|tag1 data_in VCC " "Warning: Reduced register \"rs422:inst\|tag1\" with stuck data_in port to stuck value VCC" {  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "rs422:inst\|p5~2 rs422:inst\|p5~0 " "Info: Duplicate register \"rs422:inst\|p5~2\" merged to single register \"rs422:inst\|p5~0\"" {  } {  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs422:inst\|p5~4 rs422:inst\|p5~0 " "Info: Duplicate register \"rs422:inst\|p5~4\" merged to single register \"rs422:inst\|p5~0\"" {  } {  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs422:inst\|p5~6 rs422:inst\|p5~0 " "Info: Duplicate register \"rs422:inst\|p5~6\" merged to single register \"rs422:inst\|p5~0\"" {  } {  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs422:inst\|p5~8 rs422:inst\|p5~0 " "Info: Duplicate register \"rs422:inst\|p5~8\" merged to single register \"rs422:inst\|p5~0\"" {  } {  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs422:inst\|p5~10 rs422:inst\|p5~0 " "Info: Duplicate register \"rs422:inst\|p5~10\" merged to single register \"rs422:inst\|p5~0\"" {  } {  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs422:inst\|p5~12 rs422:inst\|p5~0 " "Info: Duplicate register \"rs422:inst\|p5~12\" merged to single register \"rs422:inst\|p5~0\"" {  } {  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs422:inst\|p5~14 rs422:inst\|p5~0 " "Info: Duplicate register \"rs422:inst\|p5~14\" merged to single register \"rs422:inst\|p5~0\"" {  } {  } 0}  } {  } 0}
{ "Warning" "WOPT_ROM_FUNCTIONALITY_CHANGE_ALTSYNCRAM" "rs422:inst\|reduce_nor~68 " "Warning: Created node \"rs422:inst\|reduce_nor~68\" as a ROM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block. Power-up state differs from the original design." {  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_ROM_INFERRED" "rs422:inst\|reduce_nor~68 256 3 " "Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=256, WIDTH_A=3) from the following design logic: \"rs422:inst\|reduce_nor~68\"" {  } {  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_h0j.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_h0j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_h0j " "Info: Found entity 1: altsyncram_h0j" {  } { { "db/altsyncram_h0j.tdf" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/altsyncram_h0j.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tapg1p\[1\] GND " "Warning: Pin \"tapg1p\[1\]\" stuck at GND" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.bdf" { { 200 1160 1349 216 "tapg1p\[1..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tapg1p\[0\] GND " "Warning: Pin \"tapg1p\[0\]\" stuck at GND" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.bdf" { { 200 1160 1349 216 "tapg1p\[1..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "573 " "Info: Implemented 573 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "98 " "Info: Implemented 98 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "464 " "Info: Implemented 464 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "3 " "Info: Implemented 3 RAM segments" {  } {  } 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 09 16:09:42 2006 " "Info: Processing ended: Wed Aug 09 16:09:42 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0}  } {  } 0}