test_hier_info

FPGA串口界面调试程序,用VHDL语言实现

|test
reset => i~661.OUTPUTSELECT
reset => i~65.OUTPUTSELECT
reset => i~66.OUTPUTSELECT
reset => i~67.OUTPUTSELECT
reset => i~68.OUTPUTSELECT
reset => i~69.OUTPUTSELECT
reset => i~70.OUTPUTSELECT
reset => i~71.OUTPUTSELECT
reset => i~72.OUTPUTSELECT
reset => i~73.OUTPUTSELECT
reset => i~74.OUTPUTSELECT
reset => i~75.OUTPUTSELECT
reset => i~76.OUTPUTSELECT
reset => i~77.IN1
reset => altr_temp~0.IN1
reset => altr_temp~3.IN1
reset => altr_temp~6.IN1
reset => altr_temp~9.IN1
reset => altr_temp~12.IN1
reset => altr_temp~15.IN1
reset => altr_temp~18.IN1
reset => altr_temp~21.IN1
reset => altr_temp~24.IN1
reset => altr_temp~28.IN1
reset => altr_temp~32.IN1
reset => altr_temp~36.IN1
reset => altr_temp~40.IN1
reset => altr_temp~44.IN1
reset => altr_temp~48.IN1
reset => altr_temp~52.IN1
reset => altr_temp~56.IN1
reset => altr_temp~60.IN1
reset => altr_temp~64.IN1
reset => altr_temp~68.IN1
reset => altr_temp~72.IN1
reset => altr_temp~76.IN1
reset => altr_temp~80.IN1
reset => altr_temp~84.IN1
clk_serial => count1_1[6].CLK
clk_serial => count1_1[5].CLK
clk_serial => count1_1[4].CLK
clk_serial => count1_1[3].CLK
clk_serial => count1_1[2].CLK
clk_serial => count1_1[1].CLK
clk_serial => count1_1[0].CLK
clk_serial => p1_flag[1].CLK
clk_serial => p1_flag[0].CLK
clk_serial => D_en.CLK
clk_serial => D_busy.CLK
clk_serial => temp[7].CLK
clk_serial => temp[6].CLK
clk_serial => temp[5].CLK
clk_serial => temp[4].CLK
clk_serial => temp[3].CLK
clk_serial => temp[2].CLK
clk_serial => temp[1].CLK
clk_serial => temp[0].CLK
clk_serial => Dout[7].CLK
clk_serial => Dout[6].CLK
clk_serial => Dout[5].CLK
clk_serial => Dout[4].CLK
clk_serial => Dout[3].CLK
clk_serial => Dout[2].CLK
clk_serial => Dout[1].CLK
clk_serial => Dout[0].CLK
clk_serial => Doutp[7]~reg0.CLK
clk_serial => Doutp[6]~reg0.CLK
clk_serial => Doutp[5]~reg0.CLK
clk_serial => Doutp[4]~reg0.CLK
clk_serial => Doutp[3]~reg0.CLK
clk_serial => Doutp[2]~reg0.CLK
clk_serial => Doutp[1]~reg0.CLK
clk_serial => Doutp[0]~reg0.CLK
clk_serial => D_enp~reg0.CLK
clk_serial => D_busyp~reg0.CLK
clk_serial => count1_11p[7]~reg0.CLK
clk_serial => count1_11p[6]~reg0.CLK
clk_serial => count1_11p[5]~reg0.CLK
clk_serial => count1_11p[4]~reg0.CLK
clk_serial => count1_11p[3]~reg0.CLK
clk_serial => count1_11p[2]~reg0.CLK
clk_serial => count1_11p[1]~reg0.CLK
clk_serial => count1_11p[0]~reg0.CLK
clk_serial => STATE_1[1].CLK
clk_serial => STATE_1[0].CLK
clk_serial => Dsum1[7].CLK
clk_serial => Dsum1[6].CLK
clk_serial => Dsum1[5].CLK
clk_serial => Dsum1[4].CLK
clk_serial => Dsum1[3].CLK
clk_serial => Dsum1[2].CLK
clk_serial => Dsum1[1].CLK
clk_serial => Dsum1[0].CLK
clk_serial => RAM1[0][7].CLK
clk_serial => RAM1[0][6].CLK
clk_serial => RAM1[0][5].CLK
clk_serial => RAM1[0][4].CLK
clk_serial => RAM1[0][3].CLK
clk_serial => RAM1[0][2].CLK
clk_serial => RAM1[0][1].CLK
clk_serial => RAM1[0][0].CLK
clk_serial => RAM1[1][7].CLK
clk_serial => RAM1[1][6].CLK
clk_serial => RAM1[1][5].CLK
clk_serial => RAM1[1][4].CLK
clk_serial => RAM1[1][3].CLK
clk_serial => RAM1[1][2].CLK
clk_serial => RAM1[1][1].CLK
clk_serial => RAM1[1][0].CLK
clk_serial => RAM1[2][7].CLK
clk_serial => RAM1[2][6].CLK
clk_serial => RAM1[2][5].CLK
clk_serial => RAM1[2][4].CLK
clk_serial => RAM1[2][3].CLK
clk_serial => RAM1[2][2].CLK
clk_serial => RAM1[2][1].CLK
clk_serial => RAM1[2][0].CLK
clk_serial => RAM1[3][7].CLK
clk_serial => RAM1[3][6].CLK
clk_serial => RAM1[3][5].CLK
clk_serial => RAM1[3][4].CLK
clk_serial => RAM1[3][3].CLK
clk_serial => RAM1[3][2].CLK
clk_serial => RAM1[3][1].CLK
clk_serial => RAM1[3][0].CLK
clk_serial => RAM1[4][7].CLK
clk_serial => RAM1[4][6].CLK
clk_serial => RAM1[4][5].CLK
clk_serial => RAM1[4][4].CLK
clk_serial => RAM1[4][3].CLK
clk_serial => RAM1[4][2].CLK
clk_serial => RAM1[4][1].CLK
clk_serial => RAM1[4][0].CLK
clk_serial => RAM1[5][7].CLK
clk_serial => RAM1[5][6].CLK
clk_serial => RAM1[5][5].CLK
clk_serial => RAM1[5][4].CLK
clk_serial => RAM1[5][3].CLK
clk_serial => RAM1[5][2].CLK
clk_serial => RAM1[5][1].CLK
clk_serial => RAM1[5][0].CLK
clk_serial => RAM1[6][7].CLK
clk_serial => RAM1[6][6].CLK
clk_serial => RAM1[6][5].CLK
clk_serial => RAM1[6][4].CLK
clk_serial => RAM1[6][3].CLK
clk_serial => RAM1[6][2].CLK
clk_serial => RAM1[6][1].CLK
clk_serial => RAM1[6][0].CLK
clk_serial => RAM1[7][7].CLK
clk_serial => RAM1[7][6].CLK
clk_serial => RAM1[7][5].CLK
clk_serial => RAM1[7][4].CLK
clk_serial => RAM1[7][3].CLK
clk_serial => RAM1[7][2].CLK
clk_serial => RAM1[7][1].CLK
clk_serial => RAM1[7][0].CLK
clk_serial => LENGTH1[7].CLK
clk_serial => LENGTH1[6].CLK
clk_serial => LENGTH1[5].CLK
clk_serial => LENGTH1[4].CLK
clk_serial => LENGTH1[3].CLK
clk_serial => LENGTH1[2].CLK
clk_serial => LENGTH1[1].CLK
clk_serial => LENGTH1[0].CLK
clk_serial => STATE_1p[1]~reg0.CLK
clk_serial => STATE_1p[0]~reg0.CLK
clk_serial => Dsum1p[7]~reg0.CLK
clk_serial => Dsum1p[6]~reg0.CLK
clk_serial => Dsum1p[5]~reg0.CLK
clk_serial => Dsum1p[4]~reg0.CLK
clk_serial => Dsum1p[3]~reg0.CLK
clk_serial => Dsum1p[2]~reg0.CLK
clk_serial => Dsum1p[1]~reg0.CLK
clk_serial => Dsum1p[0]~reg0.CLK
clk_serial => LENGTH1P[7]~reg0.CLK
clk_serial => LENGTH1P[6]~reg0.CLK
clk_serial => LENGTH1P[5]~reg0.CLK
clk_serial => LENGTH1P[4]~reg0.CLK
clk_serial => LENGTH1P[3]~reg0.CLK
clk_serial => LENGTH1P[2]~reg0.CLK
clk_serial => LENGTH1P[1]~reg0.CLK
clk_serial => LENGTH1P[0]~reg0.CLK
clk_serial => dsp0_irq_0.CLK
clk_serial => dsp0_irq~reg0.CLK
clk_serial => count1_1[7].CLK
rxd => i~16.OUTPUTSELECT
rxd => i~17.OUTPUTSELECT
rxd => i~15.DATAB
rxd => i~0.OUTPUTSELECT
rxd => i~1.OUTPUTSELECT
rxd => i~2.OUTPUTSELECT
rxd => i~3.OUTPUTSELECT
rxd => i~12.DATAB
rxd => temp[7].DATAIN
rxd => temp[6].DATAIN
rxd => temp[5].DATAIN
rxd => temp[4].DATAIN
rxd => temp[3].DATAIN
rxd => temp[2].DATAIN
rxd => temp[1].DATAIN
rxd => temp[0].DATAIN
rxd => Dout[7]~0.IN0
rxd => Dout[6]~1.IN0
rxd => Dout[5]~2.IN0
rxd => Dout[4]~3.IN0
rxd => Dout[3]~4.IN0
rxd => Dout[2]~5.IN0
rxd => Dout[1]~6.IN0
rxd => Dout[0]~7.IN0
rxd => Doutp[7]~1.IN0
rxd => Doutp[6]~3.IN0
rxd => Doutp[5]~5.IN0
rxd => Doutp[4]~7.IN0
rxd => Doutp[3]~9.IN0
rxd => Doutp[2]~11.IN0
rxd => Doutp[1]~13.IN0
rxd => Doutp[0]~15.IN0
dsp0_rd => i~662.CLK
dsp0_rd => dsp0_data[14]~reg0.CLK
dsp0_rd => dsp0_data[13]~reg0.CLK
dsp0_rd => dsp0_data[12]~reg0.CLK
dsp0_rd => dsp0_data[11]~reg0.CLK
dsp0_rd => dsp0_data[10]~reg0.CLK
dsp0_rd => dsp0_data[9]~reg0.CLK
dsp0_rd => dsp0_data[8]~reg0.CLK
dsp0_rd => dsp0_data[15]~reg0.CLK
dsp0_addr[0] => Mux_2286.IN2
dsp0_addr[0] => Mux_2288.IN2
dsp0_addr[0] => Mux_2290.IN2
dsp0_addr[0] => Mux_2292.IN2
dsp0_addr[0] => Mux_2294.IN2
dsp0_addr[0] => Mux_2296.IN2
dsp0_addr[0] => Mux_2298.IN2
dsp0_addr[0] => Mux_2300.IN2
dsp0_addr[1] => Mux_2286.IN1
dsp0_addr[1] => Mux_2288.IN1
dsp0_addr[1] => Mux_2290.IN1
dsp0_addr[1] => Mux_2292.IN1
dsp0_addr[1] => Mux_2294.IN1
dsp0_addr[1] => Mux_2296.IN1
dsp0_addr[1] => Mux_2298.IN1
dsp0_addr[1] => Mux_2300.IN1
dsp0_addr[2] => Mux_2286.IN0
dsp0_addr[2] => Mux_2288.IN0
dsp0_addr[2] => Mux_2290.IN0
dsp0_addr[2] => Mux_2292.IN0
dsp0_addr[2] => Mux_2294.IN0
dsp0_addr[2] => Mux_2296.IN0
dsp0_addr[2] => Mux_2298.IN0
dsp0_addr[2] => Mux_2300.IN0
dsp0_addr[3] => i~662.DATAIN
dsp0_irq <= dsp0_irq~reg0.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[8] <= i~670.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[9] <= i~669.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[10] <= i~668.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[11] <= i~667.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[12] <= i~666.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[13] <= i~665.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[14] <= i~664.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[15] <= i~663.DB_MAX_OUTPUT_PORT_TYPE
Doutp[0] <= Doutp[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Doutp[1] <= Doutp[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Doutp[2] <= Doutp[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Doutp[3] <= Doutp[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Doutp[4] <= Doutp[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Doutp[5] <= Doutp[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Doutp[6] <= Doutp[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Doutp[7] <= Doutp[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D_enp <= D_enp~reg0.DB_MAX_OUTPUT_PORT_TYPE
D_busyp <= D_busyp~reg0.DB_MAX_OUTPUT_PORT_TYPE
STATE_1p[0] <= STATE_1p[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
STATE_1p[1] <= STATE_1p[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[0] <= Dsum1p[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[1] <= Dsum1p[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[2] <= Dsum1p[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[3] <= Dsum1p[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[4] <= Dsum1p[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[5] <= Dsum1p[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[6] <= Dsum1p[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[7] <= Dsum1p[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LENGTH1P[0] <= LENGTH1P[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LENGTH1P[1] <= LENGTH1P[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LENGTH1P[2] <= LENGTH1P[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LENGTH1P[3] <= LENGTH1P[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LENGTH1P[4] <= LENGTH1P[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LENGTH1P[5] <= LENGTH1P[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LENGTH1P[6] <= LENGTH1P[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LENGTH1P[7] <= LENGTH1P[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count1_11p[0] <= count1_11p[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count1_11p[1] <= count1_11p[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count1_11p[2] <= count1_11p[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count1_11p[3] <= count1_11p[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count1_11p[4] <= count1_11p[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count1_11p[5] <= count1_11p[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count1_11p[6] <= count1_11p[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count1_11p[7] <= count1_11p[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count1_2p[0] <= count1_2[0].DB_MAX_OUTPUT_PORT_TYPE
count1_2p[1] <= count1_2[1].DB_MAX_OUTPUT_PORT_TYPE
count1_2p[2] <= count1_2[2].DB_MAX_OUTPUT_PORT_TYPE
count1_2p[3] <= count1_2[3].DB_MAX_OUTPUT_PORT_TYPE