test_syn_hier_info

FPGA串口界面调试程序,用VHDL语言实现

|test
clk_serial => LENGTH1[2].CLK
clk_serial => LENGTH1[3].CLK
clk_serial => LENGTH1[4].CLK
clk_serial => LENGTH1[5].CLK
clk_serial => LENGTH1[6].CLK
clk_serial => LENGTH1[7].CLK
clk_serial => dsp0_irq~reg0.CLK
clk_serial => Doutp[7]~reg0.CLK
clk_serial => Doutp[6]~reg0.CLK
clk_serial => Doutp[5]~reg0.CLK
clk_serial => Doutp[4]~reg0.CLK
clk_serial => Doutp[3]~reg0.CLK
clk_serial => Doutp[2]~reg0.CLK
clk_serial => Doutp[1]~reg0.CLK
clk_serial => Doutp[0]~reg0.CLK
clk_serial => D_enp~reg0.CLK
clk_serial => D_busyp~reg0.CLK
clk_serial => STATE_1p[1]~reg0.CLK
clk_serial => STATE_1p[0]~reg0.CLK
clk_serial => Dsum1p[7]~reg0.CLK
clk_serial => Dsum1p[6]~reg0.CLK
clk_serial => Dsum1p[5]~reg0.CLK
clk_serial => Dsum1p[4]~reg0.CLK
clk_serial => Dsum1p[3]~reg0.CLK
clk_serial => Dsum1p[2]~reg0.CLK
clk_serial => Dsum1p[1]~reg0.CLK
clk_serial => Dsum1p[0]~reg0.CLK
clk_serial => LENGTH1P[7]~reg0.CLK
clk_serial => LENGTH1P[6]~reg0.CLK
clk_serial => LENGTH1P[5]~reg0.CLK
clk_serial => LENGTH1P[4]~reg0.CLK
clk_serial => LENGTH1P[3]~reg0.CLK
clk_serial => LENGTH1P[2]~reg0.CLK
clk_serial => LENGTH1P[1]~reg0.CLK
clk_serial => LENGTH1P[0]~reg0.CLK
clk_serial => count1_11p[7]~reg0.CLK
clk_serial => count1_11p[6]~reg0.CLK
clk_serial => count1_11p[5]~reg0.CLK
clk_serial => count1_11p[4]~reg0.CLK
clk_serial => count1_11p[3]~reg0.CLK
clk_serial => count1_11p[2]~reg0.CLK
clk_serial => count1_11p[1]~reg0.CLK
clk_serial => count1_11p[0]~reg0.CLK
clk_serial => dsp0_irq_0.CLK
clk_serial => temp[7].CLK
clk_serial => count1_1[5].CLK
clk_serial => count1_1[6].CLK
clk_serial => count1_1[7].CLK
clk_serial => count1_1[4].CLK
clk_serial => p1_flag[1].CLK
clk_serial => p1_flag[0].CLK
clk_serial => count1_1[1].CLK
clk_serial => count1_1[2].CLK
clk_serial => count1_1[3].CLK
clk_serial => count1_1[0].CLK
clk_serial => temp[6].CLK
clk_serial => temp[5].CLK
clk_serial => temp[4].CLK
clk_serial => temp[3].CLK
clk_serial => temp[2].CLK
clk_serial => temp[1].CLK
clk_serial => temp[0].CLK
clk_serial => D_en.CLK
clk_serial => D_busy.CLK
clk_serial => STATE_1[1].CLK
clk_serial => STATE_1[0].CLK
clk_serial => Dsum1[7].CLK
clk_serial => Dsum1[6].CLK
clk_serial => Dsum1[5].CLK
clk_serial => Dsum1[4].CLK
clk_serial => Dsum1[3].CLK
clk_serial => Dsum1[2].CLK
clk_serial => Dsum1[1].CLK
clk_serial => Dsum1[0].CLK
clk_serial => LENGTH1[1].CLK
clk_serial => LENGTH1[0].CLK
clk_serial => RAM1[5][7].CLK
clk_serial => RAM1[6][7].CLK
clk_serial => RAM1[4][7].CLK
clk_serial => RAM1[7][7].CLK
clk_serial => RAM1[2][7].CLK
clk_serial => RAM1[1][7].CLK
clk_serial => RAM1[0][7].CLK
clk_serial => RAM1[3][7].CLK
clk_serial => RAM1[5][6].CLK
clk_serial => RAM1[6][6].CLK
clk_serial => RAM1[4][6].CLK
clk_serial => RAM1[7][6].CLK
clk_serial => RAM1[2][6].CLK
clk_serial => RAM1[1][6].CLK
clk_serial => RAM1[0][6].CLK
clk_serial => RAM1[3][6].CLK
clk_serial => RAM1[5][5].CLK
clk_serial => RAM1[6][5].CLK
clk_serial => RAM1[4][5].CLK
clk_serial => RAM1[7][5].CLK
clk_serial => RAM1[2][5].CLK
clk_serial => RAM1[1][5].CLK
clk_serial => RAM1[0][5].CLK
clk_serial => RAM1[3][5].CLK
clk_serial => RAM1[5][4].CLK
clk_serial => RAM1[6][4].CLK
clk_serial => RAM1[4][4].CLK
clk_serial => RAM1[7][4].CLK
clk_serial => RAM1[2][4].CLK
clk_serial => RAM1[1][4].CLK
clk_serial => RAM1[0][4].CLK
clk_serial => RAM1[3][4].CLK
clk_serial => RAM1[5][3].CLK
clk_serial => RAM1[6][3].CLK
clk_serial => RAM1[4][3].CLK
clk_serial => RAM1[7][3].CLK
clk_serial => RAM1[2][3].CLK
clk_serial => RAM1[1][3].CLK
clk_serial => RAM1[0][3].CLK
clk_serial => RAM1[3][3].CLK
clk_serial => RAM1[5][2].CLK
clk_serial => RAM1[6][2].CLK
clk_serial => RAM1[4][2].CLK
clk_serial => RAM1[7][2].CLK
clk_serial => RAM1[2][2].CLK
clk_serial => RAM1[1][2].CLK
clk_serial => RAM1[0][2].CLK
clk_serial => RAM1[3][2].CLK
clk_serial => RAM1[5][1].CLK
clk_serial => RAM1[6][1].CLK
clk_serial => RAM1[4][1].CLK
clk_serial => RAM1[7][1].CLK
clk_serial => RAM1[2][1].CLK
clk_serial => RAM1[1][1].CLK
clk_serial => RAM1[0][1].CLK
clk_serial => RAM1[3][1].CLK
clk_serial => RAM1[5][0].CLK
clk_serial => RAM1[6][0].CLK
clk_serial => RAM1[4][0].CLK
clk_serial => RAM1[7][0].CLK
clk_serial => RAM1[2][0].CLK
clk_serial => RAM1[1][0].CLK
clk_serial => RAM1[0][0].CLK
clk_serial => RAM1[3][0].CLK
rxd => temp[7].DATAA
rxd => Doutp[7]~1.DATAA
rxd => temp[6].DATAA
rxd => temp[5].DATAA
rxd => temp[4].DATAA
rxd => temp[3].DATAA
rxd => temp[2].DATAA
rxd => temp[1].DATAA
rxd => temp[0].DATAA
rxd => Doutp[7]~81.DATAA
rxd => i~6943.DATAC
rxd => i~6969.DATAD
rxd => i~2540.DATAA
rxd => i~2107.DATAC
rxd => i~2849.DATAA
rxd => i~7035.DATAC
reset => count1_1[4].DATAA
reset => count1_1[7].DATAA
reset => count1_1[6].DATAA
reset => count1_1[5].DATAA
reset => p1_flag[1].DATAB
reset => altr_temp~58.DATAA
reset => count1_1[1].DATAA
reset => count1_1[2].DATAA
reset => count1_1[3].DATAA
reset => count1_1[0].DATAA
reset => D_en.DATAD
reset => D_busy.DATAD
reset => i~77.DATAC
reset => i~6914.DATAD
reset => i~6789.DATAA
reset => i~6794.DATAA
reset => i~6801.DATAA
reset => i~6985.DATAB
reset => i~7219.DATAA
reset => i~6798.DATAA
reset => i~713.DATAB
reset => RAM1[5][7]~102.DATAA
reset => RAM1[6][7]~109.DATAA
reset => RAM1[4][7]~116.DATAA
reset => RAM1[7][7]~123.DATAA
reset => RAM1[2][7]~130.DATAA
reset => RAM1[1][7]~137.DATAA
reset => RAM1[0][7]~144.DATAA
reset => RAM1[3][7]~151.DATAA
reset => i~7254.DATAA
dsp0_addr[0] => Mux_2286_rtl_10~0.DATAA
dsp0_addr[0] => Mux_2286_rtl_10~1.DATAB
dsp0_addr[0] => Mux_2286_rtl_9~0.DATAC
dsp0_addr[0] => Mux_2288_rtl_13~0.DATAA
dsp0_addr[0] => Mux_2288_rtl_13~1.DATAB
dsp0_addr[0] => Mux_2288_rtl_12~0.DATAC
dsp0_addr[0] => Mux_2290_rtl_16~0.DATAA
dsp0_addr[0] => Mux_2290_rtl_16~1.DATAB
dsp0_addr[0] => Mux_2290_rtl_15~0.DATAC
dsp0_addr[0] => Mux_2292_rtl_19~0.DATAA
dsp0_addr[0] => Mux_2292_rtl_19~1.DATAB
dsp0_addr[0] => Mux_2292_rtl_18~0.DATAC
dsp0_addr[0] => Mux_2294_rtl_22~0.DATAA
dsp0_addr[0] => Mux_2294_rtl_22~1.DATAB
dsp0_addr[0] => Mux_2294_rtl_21~0.DATAC
dsp0_addr[0] => Mux_2296_rtl_25~0.DATAA
dsp0_addr[0] => Mux_2296_rtl_25~1.DATAB
dsp0_addr[0] => Mux_2296_rtl_24~0.DATAC
dsp0_addr[0] => Mux_2298_rtl_28~0.DATAA
dsp0_addr[0] => Mux_2298_rtl_28~1.DATAB
dsp0_addr[0] => Mux_2298_rtl_27~0.DATAC
dsp0_addr[0] => Mux_2300_rtl_31~0.DATAA
dsp0_addr[0] => Mux_2300_rtl_31~1.DATAB
dsp0_addr[0] => Mux_2300_rtl_30~0.DATAC
dsp0_addr[1] => Mux_2286_rtl_10~0.DATAC
dsp0_addr[1] => Mux_2286_rtl_9~0.DATAA
dsp0_addr[1] => Mux_2286_rtl_9~1.DATAB
dsp0_addr[1] => Mux_2288_rtl_13~0.DATAC
dsp0_addr[1] => Mux_2288_rtl_12~0.DATAA
dsp0_addr[1] => Mux_2288_rtl_12~1.DATAB
dsp0_addr[1] => Mux_2290_rtl_16~0.DATAC
dsp0_addr[1] => Mux_2290_rtl_15~0.DATAA
dsp0_addr[1] => Mux_2290_rtl_15~1.DATAB
dsp0_addr[1] => Mux_2292_rtl_19~0.DATAC
dsp0_addr[1] => Mux_2292_rtl_18~0.DATAA
dsp0_addr[1] => Mux_2292_rtl_18~1.DATAB
dsp0_addr[1] => Mux_2294_rtl_22~0.DATAC
dsp0_addr[1] => Mux_2294_rtl_21~0.DATAA
dsp0_addr[1] => Mux_2294_rtl_21~1.DATAB
dsp0_addr[1] => Mux_2296_rtl_25~0.DATAC
dsp0_addr[1] => Mux_2296_rtl_24~0.DATAA
dsp0_addr[1] => Mux_2296_rtl_24~1.DATAB
dsp0_addr[1] => Mux_2298_rtl_28~0.DATAC
dsp0_addr[1] => Mux_2298_rtl_27~0.DATAA
dsp0_addr[1] => Mux_2298_rtl_27~1.DATAB
dsp0_addr[1] => Mux_2300_rtl_31~0.DATAC
dsp0_addr[1] => Mux_2300_rtl_30~0.DATAA
dsp0_addr[1] => Mux_2300_rtl_30~1.DATAB
dsp0_addr[2] => dsp0_data[15]~reg0.DATAD
dsp0_addr[2] => dsp0_data[14]~reg0.DATAD
dsp0_addr[2] => dsp0_data[13]~reg0.DATAD
dsp0_addr[2] => dsp0_data[12]~reg0.DATAD
dsp0_addr[2] => dsp0_data[11]~reg0.DATAD
dsp0_addr[2] => dsp0_data[10]~reg0.DATAD
dsp0_addr[2] => dsp0_data[9]~reg0.DATAD
dsp0_addr[2] => dsp0_data[8]~reg0.DATAD
dsp0_rd => dsp0_data[15]~reg0.CLK
dsp0_rd => i~662.CLK
dsp0_rd => dsp0_data[14]~reg0.CLK
dsp0_rd => dsp0_data[13]~reg0.CLK
dsp0_rd => dsp0_data[12]~reg0.CLK
dsp0_rd => dsp0_data[11]~reg0.CLK
dsp0_rd => dsp0_data[10]~reg0.CLK
dsp0_rd => dsp0_data[9]~reg0.CLK
dsp0_rd => dsp0_data[8]~reg0.CLK
dsp0_addr[3] => i~662.DATAA
dsp0_irq <= dsp0_irq~reg0
dsp0_data[15] <= dsp0_data[15]~reg0
dsp0_data[14] <= dsp0_data[14]~reg0
dsp0_data[13] <= dsp0_data[13]~reg0
dsp0_data[12] <= dsp0_data[12]~reg0
dsp0_data[11] <= dsp0_data[11]~reg0
dsp0_data[10] <= dsp0_data[10]~reg0
dsp0_data[9] <= dsp0_data[9]~reg0
dsp0_data[8] <= dsp0_data[8]~reg0
Doutp[7] <= Doutp[7]~reg0
Doutp[6] <= Doutp[6]~reg0
Doutp[5] <= Doutp[5]~reg0
Doutp[4] <= Doutp[4]~reg0
Doutp[3] <= Doutp[3]~reg0
Doutp[2] <= Doutp[2]~reg0
Doutp[1] <= Doutp[1]~reg0
Doutp[0] <= Doutp[0]~reg0
D_enp <= D_enp~reg0
D_busyp <= D_busyp~reg0
STATE_1p[1] <= STATE_1p[1]~reg0
STATE_1p[0] <= STATE_1p[0]~reg0
Dsum1p[7] <= Dsum1p[7]~reg0
Dsum1p[6] <= Dsum1p[6]~reg0
Dsum1p[5] <= Dsum1p[5]~reg0
Dsum1p[4] <= Dsum1p[4]~reg0
Dsum1p[3] <= Dsum1p[3]~reg0
Dsum1p[2] <= Dsum1p[2]~reg0
Dsum1p[1] <= Dsum1p[1]~reg0
Dsum1p[0] <= Dsum1p[0]~reg0
LENGTH1P[7] <= LENGTH1P[7]~reg0
LENGTH1P[6] <= LENGTH1P[6]~reg0
LENGTH1P[5] <= LENGTH1P[5]~reg0
LENGTH1P[4] <= LENGTH1P[4]~reg0
LENGTH1P[3] <= LENGTH1P[3]~reg0
LENGTH1P[2] <= LENGTH1P[2]~reg0
LENGTH1P[1] <= LENGTH1P[1]~reg0
LENGTH1P[0] <= LENGTH1P[0]~reg0
count1_11p[7] <= count1_11p[7]~reg0
count1_11p[6] <= count1_11p[6]~reg0
count1_11p[5] <= count1_11p[5]~reg0
count1_11p[4] <= count1_11p[4]~reg0
count1_11p[3] <= count1_11p[3]~reg0
count1_11p[2] <= count1_11p[2]~reg0
count1_11p[1] <= count1_11p[1]~reg0
count1_11p[0] <= count1_11p[0]~reg0
count1_2p[3] <= lpm_counter:count1_2_rtl_7|alt_counter_stratix:wysi_counter|safe_q[3]
count1_2p[2] <= lpm_counter:count1_2_rtl_7|alt_counter_stratix:wysi_counter|safe_q[2]
count1_2p[1] <= lpm_counter:count1_2_rtl_7|alt_counter_stratix:wysi_counter|safe_q[1]
count1_2p[0] <= lpm_counter:count1_2_rtl_7|alt_counter_stratix:wysi_counter|safe_q[0]