test.fit.rpt

FPGA串口界面调试程序,用VHDL语言实现

; Router Effort Multiplier                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                        ; Off                            ; Off                            ;
; Optimize Timing                                    ; Normal Compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing         ; On                             ; On                             ;
; Limit to One Fitting Attempt                       ; Off                            ; Off                            ;
; Final Placement Optimizations                      ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                              ; 1                              ;
; Slow Slew Rate                                     ; Off                            ; Off                            ;
; PCI I/O                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Perform Register Retiming                          ; Off                            ; Off                            ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication           ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Off                            ; Off                            ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Passive Serial      ;
; Error detection CRC                          ; Off                 ;
; Reserve Data[0] pin after configuration      ; As input tri-stated ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.pin.


+---------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                             ;
+---------------------------------------------+-----------------------------+
; Resource                                    ; Usage                       ;
+---------------------------------------------+-----------------------------+
; Total logic elements                        ; 381 / 18,460 ( 2 % )        ;
;     -- Combinational with no register       ; 149                         ;
;     -- Register only                        ; 64                          ;
;     -- Combinational with a register        ; 168                         ;
;                                             ;                             ;
; Logic element usage by number of LUT inputs ;                             ;
;     -- 4 input functions                    ; 188                         ;
;     -- 3 input functions                    ; 46                          ;
;     -- 2 input functions                    ; 76                          ;
;     -- 1 input functions                    ; 25                          ;
;     -- 0 input functions                    ; 46                          ;
;                                             ;                             ;
; Logic elements by mode                      ;                             ;
;     -- normal mode                          ; 330                         ;
;     -- arithmetic mode                      ; 51                          ;
;     -- qfbk mode                            ; 77                          ;
;     -- register cascade mode                ; 0                           ;
;     -- synchronous clear/load mode          ; 161                         ;
;     -- asynchronous clear/load mode         ; 0                           ;
;                                             ;                             ;
; Total LABs                                  ; 51 / 1,846 ( 2 % )          ;
; Logic elements in carry chains              ; 57                          ;
; User inserted logic elements                ; 0                           ;
; Virtual pins                                ; 0                           ;
; I/O pins                                    ; 105 / 427 ( 24 % )          ;
;     -- Clock pins                           ; 1 / 16 ( 6 % )              ;
; Global signals                              ; 6                           ;
; M512s                                       ; 0 / 194 ( 0 % )             ;