test.tan.rpt

FPGA串口界面调试程序,用VHDL语言实现

; Worst-case Minimum tpd                                    ; N/A       ; None                             ; 9.709 ns    ; dsp0_rd                ; RD                            ;                                            ;                                            ; 0            ;
; Clock Setup: 'CLK40M'                                     ; -7.688 ns ; 40.00 MHz ( period = 25.000 ns ) ; N/A         ; rs422:inst|D_valid1_1p ; rs422:inst|count1_2[3]        ; PLL24M:inst7|altpll:altpll_component|_clk0 ; CLK40M                                     ; 6            ;
; Clock Setup: 'PLL24M:inst7|altpll:altpll_component|_clk0' ; 2.069 ns  ; 24.00 MHz ( period = 41.666 ns ) ; N/A         ; clk:inst12|CLK200K     ; clk:inst12|count3[5]          ; CLK40M                                     ; PLL24M:inst7|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'PLL24M:inst7|altpll:altpll_component|_clk0'  ; 0.607 ns  ; 24.00 MHz ( period = 41.666 ns ) ; N/A         ; rs422:inst|count1_1[4] ; rs422:inst|count1_1[4]        ; PLL24M:inst7|altpll:altpll_component|_clk0 ; PLL24M:inst7|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'CLK40M'                                      ; 0.858 ns  ; 40.00 MHz ( period = 25.000 ns ) ; N/A         ; clk:inst12|count2[17]  ; clk:inst12|count2[17]         ; CLK40M                                     ; CLK40M                                     ; 0            ;
; Total number of failed paths                              ;           ;                                  ;             ;                        ;                               ;                                            ;                                            ; 6            ;
+-----------------------------------------------------------+-----------+----------------------------------+-------------+------------------------+-------------------------------+--------------------------------------------+--------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S20F672I7       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                            ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+----------+--------------+
; Clock Node Name                            ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset   ; Phase offset ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+----------+--------------+
; PLL24M:inst7|altpll:altpll_component|_clk0 ;                    ; PLL output ; 24.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLK40M   ; 3                     ; 5                   ; 1.209 ns ;              ;
; CLK40M                                     ;                    ; User Pin   ; 40.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A      ;              ;
; dsp0_rd                                    ;                    ; User Pin   ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A      ;              ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'PLL24M:inst7|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                   ;
+-----------------------------------------+-----------------------------------------------------+----------------------+------------------------+--------------------------------------------+--------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                 ; To                     ; From Clock                                 ; To Clock                                   ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------+------------------------+--------------------------------------------+--------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 2.069 ns                                ; None                                                ; clk:inst12|CLK200K   ; clk:inst12|count3[5]   ; CLK40M                                     ; PLL24M:inst7|altpll:altpll_component|_clk0 ; 1.209 ns                    ; 3.935 ns                  ; 1.866 ns                ;
; 2.069 ns                                ; None                                                ; clk:inst12|CLK200K   ; clk:inst12|count3[4]   ; CLK40M                                     ; PLL24M:inst7|altpll:altpll_component|_clk0 ; 1.209 ns                    ; 3.935 ns                  ; 1.866 ns                ;
; 2.069 ns                                ; None                                                ; clk:inst12|CLK200K   ; clk:inst12|count3[3]   ; CLK40M                                     ; PLL24M:inst7|altpll:altpll_component|_clk0 ; 1.209 ns                    ; 3.935 ns                  ; 1.866 ns                ;
; 2.069 ns                                ; None                                                ; clk:inst12|CLK200K   ; clk:inst12|count3[2]   ; CLK40M                                     ; PLL24M:inst7|altpll:altpll_component|_clk0 ; 1.209 ns                    ; 3.935 ns                  ; 1.866 ns                ;
; 2.069 ns                                ; None                                                ; clk:inst12|CLK200K   ; clk:inst12|count3[1]   ; CLK40M                                     ; PLL24M:inst7|altpll:altpll_component|_clk0 ; 1.209 ns                    ; 3.935 ns                  ; 1.866 ns                ;