test.tan.summary

FPGA串口界面调试程序,用VHDL语言实现

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.929 ns
From           : dsp0_addr[2]
To             : rs422:inst|dsp0_data[12]~reg0
From Clock     : 
To Clock       : dsp0_rd
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 18.742 ns
From           : rs422:inst|Dsum1[1]
To             : Dsum1p[1]
From Clock     : CLK40M
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 12.626 ns
From           : dsp0_addr[0]
To             : addrtest[0]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.302 ns
From           : RXD
To             : rs422:inst|temp[7]
From Clock     : 
To Clock       : CLK40M
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.056 ns
From           : clk:inst12|CLK_SERIAL
To             : CLK_SERIAL
From Clock     : CLK40M
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 9.709 ns
From           : dsp0_rd
To             : RD
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'CLK40M'
Slack          : -7.688 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : N/A
From           : rs422:inst|D_valid1_1p
To             : rs422:inst|count1_2[3]
From Clock     : PLL24M:inst7|altpll:altpll_component|_clk0
To Clock       : CLK40M
Failed Paths   : 6

Type           : Clock Setup: 'PLL24M:inst7|altpll:altpll_component|_clk0'
Slack          : 2.069 ns
Required Time  : 24.00 MHz ( period = 41.666 ns )
Actual Time    : N/A
From           : clk:inst12|CLK200K
To             : clk:inst12|count3[5]
From Clock     : CLK40M
To Clock       : PLL24M:inst7|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'PLL24M:inst7|altpll:altpll_component|_clk0'
Slack          : 0.607 ns
Required Time  : 24.00 MHz ( period = 41.666 ns )
Actual Time    : N/A
From           : rs422:inst|count1_1[4]
To             : rs422:inst|count1_1[4]
From Clock     : PLL24M:inst7|altpll:altpll_component|_clk0
To Clock       : PLL24M:inst7|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'CLK40M'
Slack          : 0.858 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : N/A
From           : clk:inst12|count2[17]
To             : clk:inst12|count2[17]
From Clock     : CLK40M
To Clock       : CLK40M
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 6

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