📄 devio.lst
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C51 COMPILER V7.50 DEVIO 11/03/2006 09:42:14 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE DEVIO
OBJECT MODULE PLACED IN DEVIO.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE DEVIO.c OPTIMIZE(9,SPEED) BROWSE NOAREGS DEBUG OBJECTEXTEND
line level source
1 #pragma NOIV // Do not generate interrupt vectors
2 //-----------------------------------------------------------------------------
3 // File: srcout_s.c
4 // Contents: Hooks required to implement USB peripheral function.
5 // Code written for EZUSB FX2 128-pin REVE...
6 // Firmware tested on EZUSB FX2 128-pin (CY3681 DK)
7 // Copyright (c) 2001 Cypress Semiconductor All rights reserved
8 //-----------------------------------------------------------------------------
9 #include "fx2.h"
10 #include "fx2regs.h"
11 #include "fx2sdly.h" // SYNCDELAY macro
12
13 extern BOOL GotSUD; // Received setup data flag
14 extern BOOL Sleep;
15 extern BOOL Rwuen;
16 extern BOOL Selfpwr;
17
18 BYTE Configuration; // Current configuration
19 BYTE AlternateSetting; // Alternate settings
20
21 // ...debug LEDs: accessed via movx reads only ( through CPLD )
22 xdata volatile const BYTE LED0_ON _at_ 0x8000;
23 xdata volatile const BYTE LED0_OFF _at_ 0x8100;
24 xdata volatile const BYTE LED1_ON _at_ 0x9000;
25 xdata volatile const BYTE LED1_OFF _at_ 0x9100;
26 xdata volatile const BYTE LED2_ON _at_ 0xA000;
27 xdata volatile const BYTE LED2_OFF _at_ 0xA100;
28 xdata volatile const BYTE LED3_ON _at_ 0xB000;
29 xdata volatile const BYTE LED3_OFF _at_ 0xB100;
30 // it may be worth noting here that the default monitor loads at 0xC000
31
32 // use this global variable when (de)asserting debug LEDs...
33 BYTE ledX_rdvar = 0x00;
34
35 //BYTE xdata Digit[] = { 0xc0, 0xf9, 0xa4, 0xb0, 0x99, 0x92, 0x82, 0xf8, 0x80, 0x98, 0x88, 0x83, 0xc6, 0xa
-1, 0x86, 0x8e };
36 BYTE xdata Digit[] = { 0xC0, 0xf9, 0x64, 0x46, 0x4b, 0x52, 0x50, 0xc7, 0x40, 0x43, 0x41, 0x58, 0xf0, 0x4c,
- 0x70, 0x71 };
37
38 #define BTN_ADDR 0x38
39 #define LED_ADDR 0x39
40
41 BYTE num = 0x0f;
42 BYTE display = TRUE;
43
44 sbit PA0 = IOA ^ 0;
45 sbit PA1 = IOA ^ 1;
46 sbit PA2 = IOA ^ 2;
47 sbit PA3 = IOA ^ 3;
48 sbit PA4 = IOA ^ 4;
49 sbit PA5 = IOA ^ 5;
50 sbit PA6 = IOA ^ 6;
51 sbit PA7 = IOA ^ 7;
52
53
C51 COMPILER V7.50 DEVIO 11/03/2006 09:42:14 PAGE 2
54 sbit PB0 = IOB ^ 0;
55 sbit PB1 = IOB ^ 1;
56 sbit PB2 = IOB ^ 2;
57 sbit PB3 = IOB ^ 3;
58 sbit PB4 = IOB ^ 4;
59 sbit PB5 = IOB ^ 5;
60 sbit PB6 = IOB ^ 6;
61 sbit PB7 = IOB ^ 7;
62
63 #define KEY_WAKEUP 0
64 #define KEY_F1 1
65 #define KEY_F2 2
66 #define KEY_F3 3
67
68 //-----------------------------------------------------------------------------
69 // Task Dispatcher hooks
70 // The following hooks are called by the task dispatcher.
71 //-----------------------------------------------------------------------------
72 void TD_Init( void )
73 { // Called once at startup
74 1
75 1 CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation
76 1 // CLKOE=0, don't drive CLKOUT
77 1
78 1 IFCONFIG = 0xC0;
79 1 // IFCLKSRC=1 , FIFOs executes on internal clk source
80 1 // xMHz=1 , 48MHz internal clk rate
81 1 // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
82 1 // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
83 1 // ASYNC=1 , master samples asynchronous
84 1 // GSTATE=0 , Don't drive GPIF states out on PORTE[2:0], debug WF
85 1 // IFCFG[1:0]=11, FX2 in slave FIFO mode
86 1
87 1
88 1 // Registers which require a synchronization delay, see section 15.14
89 1 // FIFORESET FIFOPINPOLAR
90 1 // INPKTEND OUTPKTEND
91 1 // EPxBCH:L REVCTL
92 1 // GPIFTCB3 GPIFTCB2
93 1 // GPIFTCB1 GPIFTCB0
94 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
95 1 // EPxFIFOCFG EPxGPIFFLGSEL
96 1 // PINFLAGSxx EPxFIFOIRQ
97 1 // EPxFIFOIE GPIFIRQ
98 1 // GPIFIE GPIFADRH:L
99 1 // UDMACRCH:L EPxGPIFTRIG
100 1 // GPIFTRIG
101 1
102 1 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
103 1 // ...these have been replaced by GPIFTC[B3:B0] registers
104 1
105 1 SYNCDELAY; // see TRM section 15.14
106 1 REVCTL = 0x01; // use enhanced packet handling
107 1
108 1 // NOTE: when using "enhanced packet handling" feature (REVCTL.0=1)
109 1 // ...the core functions as follows:
110 1 // - OUTPKTEND is used to skip/commit OUT pkt.
111 1 // - INPKTEND is used to skip/commit IN pkt.
112 1 // - EPxBCH/L is used to
113 1 // - commit cpu sourced pkt.
114 1 // - modify length of an OUT pkt.
115 1 // - cpu can not source an OUT pkt in "AUTOOUT" mode
C51 COMPILER V7.50 DEVIO 11/03/2006 09:42:14 PAGE 3
116 1 // - see cpu source out pkt method in BOOL DR_VendorCmnd(); ...
117 1
118 1 // EP2 512 BULK OUT 4x
119 1 SYNCDELAY; //
120 1 EP2CFG = 0xA0; // BUF[1:0]=00 for 4x buffering
121 1
122 1 // EP6 512 BULK IN 4x
123 1 SYNCDELAY; //
124 1 EP6CFG = 0xE0; // BUF[1:0]=00 for 4x buffering
125 1
126 1 // EP4 and EP8 are not used in this implementation...
127 1 SYNCDELAY; //
128 1 EP4CFG = 0x20; // clear valid bit
129 1 SYNCDELAY; //
130 1 EP8CFG = 0x60; // clear valid bit
131 1
132 1 SYNCDELAY; //
133 1 FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
134 1 SYNCDELAY; //
135 1 FIFORESET = 0x02; // reset, FIFO 2
136 1 SYNCDELAY; //
137 1 FIFORESET = 0x04; // reset, FIFO 4
138 1 SYNCDELAY; //
139 1 FIFORESET = 0x06; // reset, FIFO 6
140 1 SYNCDELAY; //
141 1 FIFORESET = 0x08; // reset, FIFO 8
142 1 SYNCDELAY; //
143 1 FIFORESET = 0x00; // deactivate NAK-ALL
144 1
145 1 // 8-bit bus (WORDWIDE=0)...
146 1
147 1 // use manual out mode...
148 1 SYNCDELAY; //
149 1 EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=0
150 1
151 1 SYNCDELAY; //
152 1 OUTPKTEND = 0x82; // arm first buffer
153 1 SYNCDELAY; //
154 1 OUTPKTEND = 0x82; // arm second buffer
155 1 SYNCDELAY; //
156 1 OUTPKTEND = 0x82; // arm third buffer
157 1 SYNCDELAY; //
158 1 OUTPKTEND = 0x82; // arm fourth buffer
159 1
160 1 // use auto in mode
161 1 SYNCDELAY; //
162 1 EP6FIFOCFG = 0x0C; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0
163 1 OEA=0x0F;
164 1 IOA=0xff;
165 1 OEB=0x00;
166 1 }
167
168 void TD_Poll( void )
169 { // Called repeatedly while the device is idle
170 1
171 1 // see BOOL DR_VendorCmnd( void );
172 1 // ...core "auto" commits pkts using EP6AUTOINLENH/L value
173 1
174 1
175 1 OEA=0x0F;
176 1 if (PB0==0)
177 1 {
C51 COMPILER V7.50 DEVIO 11/03/2006 09:42:14 PAGE 4
178 2 PA0=1;PA1=1;PA2=0;
179 2 }
180 1 else if (PB1==0)
181 1 {
182 2 PA0=1;PA1=0;PA2=1;
183 2 }
184 1 else if (PB2==0)
185 1 {
186 2 PA0=0;PA1=1;PA2=1;PA3=1;
187 2 }
188 1
189 1 }
190
191 BOOL TD_Suspend( void )
192 { // Called before the device goes into suspend mode
193 1 return( TRUE );
194 1 }
195
196 BOOL TD_Resume( void )
197 { // Called after the device resumes
198 1 return( TRUE );
199 1 }
200
201 //-----------------------------------------------------------------------------
202 // Device Request hooks
203 // The following hooks are called by the end point 0 device request parser.
204 //-----------------------------------------------------------------------------
205 BOOL DR_GetDescriptor( void )
206 {
207 1 return( TRUE );
208 1 }
209
210 BOOL DR_SetConfiguration( void )
211 { // Called when a Set Configuration command is received
212 1
213 1 if( EZUSB_HIGHSPEED( ) )
214 1 { // ...FX2 in high speed mode
215 2 SYNCDELAY; //
216 2 EP6AUTOINLENH = 0x02; // set core AUTO commit len = 512 bytes
217 2 SYNCDELAY; //
218 2 EP6AUTOINLENL = 0x00;
219 2 SYNCDELAY; //
220 2 }
221 1 else
222 1 { // ...FX2 in full speed mode
223 2 SYNCDELAY; //
224 2 EP6AUTOINLENH = 0x00; // set core AUTO commit len = 64 bytes
225 2 SYNCDELAY; //
226 2 EP6AUTOINLENL = 0x40;
227 2 SYNCDELAY; //
228 2 }
229 1
230 1 Configuration = SETUPDAT[ 2 ];
231 1 return( TRUE ); // Handled by user code
232 1 }
233
234 BOOL DR_GetConfiguration( void )
235 { // Called when a Get Configuration command is received
236 1 EP0BUF[ 0 ] = Configuration;
237 1 EP0BCH = 0;
238 1 EP0BCL = 1;
239 1 return(TRUE); // Handled by user code
C51 COMPILER V7.50 DEVIO 11/03/2006 09:42:14 PAGE 5
240 1 }
241
242 BOOL DR_SetInterface( void )
243 { // Called when a Set Interface command is received
244 1 AlternateSetting = SETUPDAT[ 2 ];
245 1 return( TRUE ); // Handled by user code
246 1 }
247
248 BOOL DR_GetInterface( void )
249 { // Called when a Set Interface command is received
250 1 EP0BUF[ 0 ] = AlternateSetting;
251 1 EP0BCH = 0;
252 1 EP0BCL = 1;
253 1 return( TRUE ); // Handled by user code
254 1 }
255
256 BOOL DR_GetStatus( void )
257 {
258 1 return( TRUE );
259 1 }
260
261 BOOL DR_ClearFeature( void )
262 {
263 1 return( TRUE );
264 1 }
265
266 BOOL DR_SetFeature( void )
267 {
268 1 return( TRUE );
269 1 }
270
271 #define VX_B2 0xB2 // turn ON debug LEDs...
272 #define VX_B3 0xB3 // turn OFF debug LEDs...
273
274 #define VX_B7 0xB7 // re-initialize, call TD_Init( );
275 #define VX_B8 0xB8 // do a "soft reset", vector to org 00h
276 #define VX_BA 0xBA // commit out pkt. new way
277 #define VX_BB 0xBB // commit in pkt. new way
278 #define VX_C2 0xC2 // source out pkt.
279
280
281 #define VX_BC 0xBC // turn OFF debug LEDs...
282 #define VX_BD 0xBD // turn OFF debug LEDs...
283 #define VX_BE 0xBE // turn OFF debug LEDs...
284 #define VX_BF 0xBF // turn OFF debug LEDs...
285
286 #define VX_C3 0xC3 // turn OFF debug LEDs...
287
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