📄 devio.c
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#pragma NOIV // Do not generate interrupt vectors
//-----------------------------------------------------------------------------
// File: srcout_s.c
// Contents: Hooks required to implement USB peripheral function.
// Code written for EZUSB FX2 128-pin REVE...
// Firmware tested on EZUSB FX2 128-pin (CY3681 DK)
// Copyright (c) 2001 Cypress Semiconductor All rights reserved
//-----------------------------------------------------------------------------
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h" // SYNCDELAY macro
extern BOOL GotSUD; // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;
BYTE Configuration; // Current configuration
BYTE AlternateSetting; // Alternate settings
// ...debug LEDs: accessed via movx reads only ( through CPLD )
xdata volatile const BYTE LED0_ON _at_ 0x8000;
xdata volatile const BYTE LED0_OFF _at_ 0x8100;
xdata volatile const BYTE LED1_ON _at_ 0x9000;
xdata volatile const BYTE LED1_OFF _at_ 0x9100;
xdata volatile const BYTE LED2_ON _at_ 0xA000;
xdata volatile const BYTE LED2_OFF _at_ 0xA100;
xdata volatile const BYTE LED3_ON _at_ 0xB000;
xdata volatile const BYTE LED3_OFF _at_ 0xB100;
// it may be worth noting here that the default monitor loads at 0xC000
// use this global variable when (de)asserting debug LEDs...
BYTE ledX_rdvar = 0x00;
//BYTE xdata Digit[] = { 0xc0, 0xf9, 0xa4, 0xb0, 0x99, 0x92, 0x82, 0xf8, 0x80, 0x98, 0x88, 0x83, 0xc6, 0xa1, 0x86, 0x8e };
BYTE xdata Digit[] = { 0xC0, 0xf9, 0x64, 0x46, 0x4b, 0x52, 0x50, 0xc7, 0x40, 0x43, 0x41, 0x58, 0xf0, 0x4c, 0x70, 0x71 };
#define BTN_ADDR 0x38
#define LED_ADDR 0x39
BYTE num = 0x0f;
BYTE display = TRUE;
sbit PA0 = IOA ^ 0;
sbit PA1 = IOA ^ 1;
sbit PA2 = IOA ^ 2;
sbit PA3 = IOA ^ 3;
sbit PA4 = IOA ^ 4;
sbit PA5 = IOA ^ 5;
sbit PA6 = IOA ^ 6;
sbit PA7 = IOA ^ 7;
sbit PB0 = IOB ^ 0;
sbit PB1 = IOB ^ 1;
sbit PB2 = IOB ^ 2;
sbit PB3 = IOB ^ 3;
sbit PB4 = IOB ^ 4;
sbit PB5 = IOB ^ 5;
sbit PB6 = IOB ^ 6;
sbit PB7 = IOB ^ 7;
#define KEY_WAKEUP 0
#define KEY_F1 1
#define KEY_F2 2
#define KEY_F3 3
//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
void TD_Init( void )
{ // Called once at startup
CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation
// CLKOE=0, don't drive CLKOUT
IFCONFIG = 0xC0;
// IFCLKSRC=1 , FIFOs executes on internal clk source
// xMHz=1 , 48MHz internal clk rate
// IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
// ASYNC=1 , master samples asynchronous
// GSTATE=0 , Don't drive GPIF states out on PORTE[2:0], debug WF
// IFCFG[1:0]=11, FX2 in slave FIFO mode
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
SYNCDELAY; // see TRM section 15.14
REVCTL = 0x01; // use enhanced packet handling
// NOTE: when using "enhanced packet handling" feature (REVCTL.0=1)
// ...the core functions as follows:
// - OUTPKTEND is used to skip/commit OUT pkt.
// - INPKTEND is used to skip/commit IN pkt.
// - EPxBCH/L is used to
// - commit cpu sourced pkt.
// - modify length of an OUT pkt.
// - cpu can not source an OUT pkt in "AUTOOUT" mode
// - see cpu source out pkt method in BOOL DR_VendorCmnd(); ...
// EP2 512 BULK OUT 4x
SYNCDELAY; //
EP2CFG = 0xA0; // BUF[1:0]=00 for 4x buffering
// EP6 512 BULK IN 4x
SYNCDELAY; //
EP6CFG = 0xE0; // BUF[1:0]=00 for 4x buffering
// EP4 and EP8 are not used in this implementation...
SYNCDELAY; //
EP4CFG = 0x20; // clear valid bit
SYNCDELAY; //
EP8CFG = 0x60; // clear valid bit
SYNCDELAY; //
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; //
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
// 8-bit bus (WORDWIDE=0)...
// use manual out mode...
SYNCDELAY; //
EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=0
SYNCDELAY; //
OUTPKTEND = 0x82; // arm first buffer
SYNCDELAY; //
OUTPKTEND = 0x82; // arm second buffer
SYNCDELAY; //
OUTPKTEND = 0x82; // arm third buffer
SYNCDELAY; //
OUTPKTEND = 0x82; // arm fourth buffer
// use auto in mode
SYNCDELAY; //
EP6FIFOCFG = 0x0C; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0
OEA=0x0F;
IOA=0xff;
OEB=0x00;
}
void TD_Poll( void )
{ // Called repeatedly while the device is idle
// see BOOL DR_VendorCmnd( void );
// ...core "auto" commits pkts using EP6AUTOINLENH/L value
OEA=0x0F;
if (PB0==0)
{
PA0=1;PA1=1;PA2=0;
}
else if (PB1==0)
{
PA0=1;PA1=0;PA2=1;
}
else if (PB2==0)
{
PA0=0;PA1=1;PA2=1;PA3=1;
}
}
BOOL TD_Suspend( void )
{ // Called before the device goes into suspend mode
return( TRUE );
}
BOOL TD_Resume( void )
{ // Called after the device resumes
return( TRUE );
}
//-----------------------------------------------------------------------------
// Device Request hooks
// The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor( void )
{
return( TRUE );
}
BOOL DR_SetConfiguration( void )
{ // Called when a Set Configuration command is received
if( EZUSB_HIGHSPEED( ) )
{ // ...FX2 in high speed mode
SYNCDELAY; //
EP6AUTOINLENH = 0x02; // set core AUTO commit len = 512 bytes
SYNCDELAY; //
EP6AUTOINLENL = 0x00;
SYNCDELAY; //
}
else
{ // ...FX2 in full speed mode
SYNCDELAY; //
EP6AUTOINLENH = 0x00; // set core AUTO commit len = 64 bytes
SYNCDELAY; //
EP6AUTOINLENL = 0x40;
SYNCDELAY; //
}
Configuration = SETUPDAT[ 2 ];
return( TRUE ); // Handled by user code
}
BOOL DR_GetConfiguration( void )
{ // Called when a Get Configuration command is received
EP0BUF[ 0 ] = Configuration;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_SetInterface( void )
{ // Called when a Set Interface command is received
AlternateSetting = SETUPDAT[ 2 ];
return( TRUE ); // Handled by user code
}
BOOL DR_GetInterface( void )
{ // Called when a Set Interface command is received
EP0BUF[ 0 ] = AlternateSetting;
EP0BCH = 0;
EP0BCL = 1;
return( TRUE ); // Handled by user code
}
BOOL DR_GetStatus( void )
{
return( TRUE );
}
BOOL DR_ClearFeature( void )
{
return( TRUE );
}
BOOL DR_SetFeature( void )
{
return( TRUE );
}
#define VX_B2 0xB2 // turn ON debug LEDs...
#define VX_B3 0xB3 // turn OFF debug LEDs...
#define VX_B7 0xB7 // re-initialize, call TD_Init( );
#define VX_B8 0xB8 // do a "soft reset", vector to org 00h
#define VX_BA 0xBA // commit out pkt. new way
#define VX_BB 0xBB // commit in pkt. new way
#define VX_C2 0xC2 // source out pkt.
#define VX_BC 0xBC // turn OFF debug LEDs...
#define VX_BD 0xBD // turn OFF debug LEDs...
#define VX_BE 0xBE // turn OFF debug LEDs...
#define VX_BF 0xBF // turn OFF debug LEDs...
#define VX_C3 0xC3 // turn OFF debug LEDs...
// Core uses bRequest value 0xA0 for Anchor downloads/uploads...
// Cypress Semiconductor reserves bRequest values 0xA1 through 0xAF...
// Your implementation should not use the above bRequest values...
// Also, previous fw.c versions trap all bRequest values 0x00 through 0x0F...
//
// bRequest value: SETUPDAT[1]
// standard, 0x00 through 0x0F
//
// bmRequest value: SETUPDAT[0]
// standard, 0x80 IN Token
// vendor, 0xC0 IN Token
// class, 0xA0 IN Token
// standard, 0x00 OUT Token
// vendor, 0x40 OUT Token
// class, 0x60 OUT Token
BOOL DR_VendorCmnd( void )
{
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
switch( SETUPDAT[ 1 ] )
{
case VX_B2:
{ // turn OFF debug LEDs...
ledX_rdvar = LED0_ON; // visual
ledX_rdvar = LED1_ON; // visual
ledX_rdvar = LED2_ON; // visual
ledX_rdvar = LED3_ON; // visual
*EP0BUF = VX_B2;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break;
}
case VX_B3:
{ // turn OFF debug LEDs...
ledX_rdvar = LED0_OFF; // visual
ledX_rdvar = LED1_OFF; // visual
ledX_rdvar = LED2_OFF; // visual
ledX_rdvar = LED3_OFF; // visual
*EP0BUF = VX_B3;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break;
}
case VX_BC:
{ // turn OFF debug LEDs...
*EP0BUF = num;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break;
}
default:
{
ledX_rdvar = LED3_ON; // debug visual, stuck "ON" to warn developer...
return( FALSE ); // no error; command handled OK
}
}
return( FALSE ); // no error; command handled OK
}
//-----------------------------------------------------------------------------
// USB Interrupt Handlers
// The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------
// Setup Data Available Interrupt Handler
void ISR_Sudav( void ) interrupt 0
{
GotSUD = TRUE; // Set flag
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUDAV; // Clear SUDAV IRQ
}
// Setup Token Interrupt Handler
void ISR_Sutok( void ) interrupt 0
{
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUTOK; // Clear SUTOK IRQ
}
void ISR_Sof( void ) interrupt 0
{
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSOF; // Clear SOF IRQ
}
void ISR_Ures( void ) interrupt 0
{
if ( EZUSB_HIGHSPEED( ) )
{
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
}
else
{
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}
EZUSB_IRQ_CLEAR( );
USBIRQ = bmURES; // Clear URES IRQ
}
void ISR_Susp( void ) interrupt 0
{
Sleep = TRUE;
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUSP;
}
void ISR_Highspeed( void ) interrupt 0
{
if ( EZUSB_HIGHSPEED( ) )
{
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
}
else
{
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}
EZUSB_IRQ_CLEAR( );
USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack( void ) interrupt 0
{
}
void ISR_Stub( void ) interrupt 0
{
}
void ISR_Ep0in( void ) interrupt 0
{
}
void ISR_Ep0out( void ) interrupt 0
{
}
void ISR_Ep1in( void ) interrupt 0
{
}
void ISR_Ep1out( void ) interrupt 0
{
}
void ISR_Ep2inout( void ) interrupt 0
{
}
void ISR_Ep4inout( void ) interrupt 0
{
}
void ISR_Ep6inout( void ) interrupt 0
{
}
void ISR_Ep8inout( void ) interrupt 0
{
}
void ISR_Ibn( void ) interrupt 0
{
}
void ISR_Ep0pingnak( void ) interrupt 0
{
}
void ISR_Ep1pingnak( void ) interrupt 0
{
}
void ISR_Ep2pingnak( void ) interrupt 0
{
}
void ISR_Ep4pingnak( void ) interrupt 0
{
}
void ISR_Ep6pingnak( void ) interrupt 0
{
}
void ISR_Ep8pingnak( void ) interrupt 0
{
}
void ISR_Errorlimit( void ) interrupt 0
{
}
void ISR_Ep2piderror( void ) interrupt 0
{
}
void ISR_Ep4piderror( void ) interrupt 0
{
}
void ISR_Ep6piderror( void ) interrupt 0
{
}
void ISR_Ep8piderror( void ) interrupt 0
{
}
void ISR_Ep2pflag( void ) interrupt 0
{
}
void ISR_Ep4pflag( void ) interrupt 0
{
}
void ISR_Ep6pflag( void ) interrupt 0
{
}
void ISR_Ep8pflag( void ) interrupt 0
{
}
void ISR_Ep2eflag( void ) interrupt 0
{
}
void ISR_Ep4eflag( void ) interrupt 0
{
}
void ISR_Ep6eflag( void ) interrupt 0
{
}
void ISR_Ep8eflag( void ) interrupt 0
{
}
void ISR_Ep2fflag( void ) interrupt 0
{
}
void ISR_Ep4fflag( void ) interrupt 0
{
}
void ISR_Ep6fflag( void ) interrupt 0
{
}
void ISR_Ep8fflag( void ) interrupt 0
{
}
void ISR_GpifComplete( void ) interrupt 0
{
}
void ISR_GpifWaveform( void ) interrupt 0
{
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