myfx2.fit.rpt

FPGA与USB通信的测试代码

Fitter report for MYFX2
Fri Nov 03 08:53:18 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. LogicLock Region Resource Usage
  9. Input Pins
 10. Output Pins
 11. Bidir Pins
 12. I/O Bank Usage
 13. All Package Pins
 14. Output Pin Default Load For Reported TCO
 15. Fitter Resource Utilization by Entity
 16. Delay Chain Summary
 17. Pad To Core Delay Chain Fanout
 18. Control Signals
 19. Global & Other Fast Signals
 20. Non-Global High Fan-Out Signals
 21. Interconnect Usage Summary
 22. LAB Logic Elements
 23. LAB-wide Signals
 24. LAB Signals Sourced
 25. LAB Signals Sourced Out
 26. LAB Distinct Inputs
 27. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Fri Nov 03 08:53:18 2006    ;
; Quartus II Version    ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name         ; MYFX2                                    ;
; Top-level Entity Name ; MYFX2                                    ;
; Family                ; Cyclone                                  ;
; Device                ; EP1C6Q240C8                              ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 25 / 5,980 ( < 1 % )                     ;
; Total pins            ; 142 / 185 ( 76 % )                       ;
; Total virtual pins    ; 0                                        ;
; Total memory bits     ; 0 / 92,160 ( 0 % )                       ;
; Total PLLs            ; 0 / 2 ( 0 % )                            ;
+-----------------------+------------------------------------------+


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; Fitter Settings                                                                                                      ;