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📄 myfx2.tan.qmsg

📁 FPGA与USB通信的测试代码
💻 QMSG
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{ "Info" "ITDB_TSU_RESULT" "LDT nRESET MMCLK -1.970 ns register " "Info: tsu for register \"LDT\" (data pin = \"nRESET\", clock pin = \"MMCLK\") is -1.970 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.450 ns + Longest pin register " "Info: + Longest pin to register delay is 3.450 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns nRESET 1 PIN PIN_131 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_131; Fanout = 25; PIN Node = 'nRESET'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { nRESET } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.114 ns) + CELL(0.867 ns) 3.450 ns LDT 2 REG LC_X31_Y14_N9 2 " "Info: 2: + IC(1.114 ns) + CELL(0.867 ns) = 3.450 ns; Loc. = LC_X31_Y14_N9; Fanout = 2; REG Node = 'LDT'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "1.981 ns" { nRESET LDT } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 67.71 % " "Info: Total cell delay = 2.336 ns ( 67.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.114 ns 32.29 % " "Info: Total interconnect delay = 1.114 ns ( 32.29 % )" {  } {  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "3.450 ns" { nRESET LDT } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.450 ns" { nRESET nRESET~out0 LDT } { 0.000ns 0.000ns 1.114ns } { 0.000ns 1.469ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MMCLK destination 5.457 ns - Shortest register " "Info: - Shortest clock path from clock \"MMCLK\" to destination register is 5.457 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MMCLK 1 CLK PIN_153 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 25; CLK Node = 'MMCLK'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { MMCLK } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.764 ns) + CELL(0.935 ns) 4.168 ns Mega_cnt\[23\] 2 REG LC_X31_Y14_N6 2 " "Info: 2: + IC(1.764 ns) + CELL(0.935 ns) = 4.168 ns; Loc. = LC_X31_Y14_N6; Fanout = 2; REG Node = 'Mega_cnt\[23\]'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "2.699 ns" { MMCLK Mega_cnt[23] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.578 ns) + CELL(0.711 ns) 5.457 ns LDT 3 REG LC_X31_Y14_N9 2 " "Info: 3: + IC(0.578 ns) + CELL(0.711 ns) = 5.457 ns; Loc. = LC_X31_Y14_N9; Fanout = 2; REG Node = 'LDT'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "1.289 ns" { Mega_cnt[23] LDT } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 57.08 % " "Info: Total cell delay = 3.115 ns ( 57.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.342 ns 42.92 % " "Info: Total interconnect delay = 2.342 ns ( 42.92 % )" {  } {  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "5.457 ns" { MMCLK Mega_cnt[23] LDT } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.457 ns" { MMCLK MMCLK~out0 Mega_cnt[23] LDT } { 0.000ns 0.000ns 1.764ns 0.578ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "3.450 ns" { nRESET LDT } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.450 ns" { nRESET nRESET~out0 LDT } { 0.000ns 0.000ns 1.114ns } { 0.000ns 1.469ns 0.867ns } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "5.457 ns" { MMCLK Mega_cnt[23] LDT } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.457 ns" { MMCLK MMCLK~out0 Mega_cnt[23] LDT } { 0.000ns 0.000ns 1.764ns 0.578ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "MMCLK LED\[3\] LDT 10.080 ns register " "Info: tco from clock \"MMCLK\" to destination pin \"LED\[3\]\" through register \"LDT\" is 10.080 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MMCLK source 5.457 ns + Longest register " "Info: + Longest clock path from clock \"MMCLK\" to source register is 5.457 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MMCLK 1 CLK PIN_153 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 25; CLK Node = 'MMCLK'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { MMCLK } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.764 ns) + CELL(0.935 ns) 4.168 ns Mega_cnt\[23\] 2 REG LC_X31_Y14_N6 2 " "Info: 2: + IC(1.764 ns) + CELL(0.935 ns) = 4.168 ns; Loc. = LC_X31_Y14_N6; Fanout = 2; REG Node = 'Mega_cnt\[23\]'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "2.699 ns" { MMCLK Mega_cnt[23] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.578 ns) + CELL(0.711 ns) 5.457 ns LDT 3 REG LC_X31_Y14_N9 2 " "Info: 3: + IC(0.578 ns) + CELL(0.711 ns) = 5.457 ns; Loc. = LC_X31_Y14_N9; Fanout = 2; REG Node = 'LDT'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "1.289 ns" { Mega_cnt[23] LDT } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 57.08 % " "Info: Total cell delay = 3.115 ns ( 57.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.342 ns 42.92 % " "Info: Total interconnect delay = 2.342 ns ( 42.92 % )" {  } {  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "5.457 ns" { MMCLK Mega_cnt[23] LDT } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.457 ns" { MMCLK MMCLK~out0 Mega_cnt[23] LDT } { 0.000ns 0.000ns 1.764ns 0.578ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.399 ns + Longest register pin " "Info: + Longest register to pin delay is 4.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LDT 1 REG LC_X31_Y14_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y14_N9; Fanout = 2; REG Node = 'LDT'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { LDT } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.275 ns) + CELL(2.124 ns) 4.399 ns LED\[3\] 2 PIN PIN_180 0 " "Info: 2: + IC(2.275 ns) + CELL(2.124 ns) = 4.399 ns; Loc. = PIN_180; Fanout = 0; PIN Node = 'LED\[3\]'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "4.399 ns" { LDT LED[3] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 34 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 48.28 % " "Info: Total cell delay = 2.124 ns ( 48.28 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.275 ns 51.72 % " "Info: Total interconnect delay = 2.275 ns ( 51.72 % )" {  } {  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "4.399 ns" { LDT LED[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.399 ns" { LDT LED[3] } { 0.000ns 2.275ns } { 0.000ns 2.124ns } } }  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "5.457 ns" { MMCLK Mega_cnt[23] LDT } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.457 ns" { MMCLK MMCLK~out0 Mega_cnt[23] LDT } { 0.000ns 0.000ns 1.764ns 0.578ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "4.399 ns" { LDT LED[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.399 ns" { LDT LED[3] } { 0.000ns 2.275ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "PA\[0\] LED\[0\] 13.088 ns Longest " "Info: Longest tpd from source pin \"PA\[0\]\" to destination pin \"LED\[0\]\" is 13.088 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns PA\[0\] 1 PIN PIN_44 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_44; Fanout = 1; PIN Node = 'PA\[0\]'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { PA[0] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(9.511 ns) + CELL(2.108 ns) 13.088 ns LED\[0\] 2 PIN PIN_183 0 " "Info: 2: + IC(9.511 ns) + CELL(2.108 ns) = 13.088 ns; Loc. = PIN_183; Fanout = 0; PIN Node = 'LED\[0\]'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "11.619 ns" { PA[0] LED[0] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 34 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.577 ns 27.33 % " "Info: Total cell delay = 3.577 ns ( 27.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.511 ns 72.67 % " "Info: Total interconnect delay = 9.511 ns ( 72.67 % )" {  } {  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "13.088 ns" { PA[0] LED[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.088 ns" { PA[0] PA[0]~out0 LED[0] } { 0.000ns 0.000ns 9.511ns } { 0.000ns 1.469ns 2.108ns } } }  } 0}
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