📄 myfx2.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "MMCLK " "Info: Assuming node \"MMCLK\" is an undefined clock" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 31 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "MMCLK" } } } } } 0} } { } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Mega_cnt\[23\] " "Info: Detected ripple clock \"Mega_cnt\[23\]\" as buffer" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Mega_cnt\[23\]" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "MMCLK register register Mega_cnt\[3\] Mega_cnt\[22\] 275.03 MHz Internal " "Info: Clock \"MMCLK\" Internal fmax is restricted to 275.03 MHz between source register \"Mega_cnt\[3\]\" and destination register \"Mega_cnt\[22\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.835 ns + Longest register register " "Info: + Longest register to register delay is 2.835 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Mega_cnt\[3\] 1 REG LC_X31_Y16_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y16_N6; Fanout = 3; REG Node = 'Mega_cnt\[3\]'" { } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { Mega_cnt[3] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.575 ns) 1.098 ns Mega_cnt\[3\]~249COUT1_267 2 COMB LC_X31_Y16_N6 2 " "Info: 2: + IC(0.523 ns) + CELL(0.575 ns) = 1.098 ns; Loc. = LC_X31_Y16_N6; Fanout = 2; COMB Node = 'Mega_cnt\[3\]~249COUT1_267'" { } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "1.098 ns" { Mega_cnt[3] Mega_cnt[3]~249COUT1_267 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.178 ns Mega_cnt\[4\]~245COUT1_268 3 COMB LC_X31_Y16_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.178 ns; Loc. = LC_X31_Y16_N7; Fanout = 2; COMB Node = 'Mega_cnt\[4\]~245COUT1_268'" { } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.080 ns" { Mega_cnt[3]~249COUT1_267 Mega_cnt[4]~245COUT1_268 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.258 ns Mega_cnt\[5\]~241COUT1_269 4 COMB LC_X31_Y16_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.258 ns; Loc. = LC_X31_Y16_N8; Fanout = 2; COMB Node = 'Mega_cnt\[5\]~241COUT1_269'" { } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.080 ns" { Mega_cnt[4]~245COUT1_268 Mega_cnt[5]~241COUT1_269 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.516 ns Mega_cnt\[6\]~237 5 COMB LC_X31_Y16_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.516 ns; Loc. = LC_X31_Y16_N9; Fanout = 6; COMB Node = 'Mega_cnt\[6\]~237'" { } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.258 ns" { Mega_cnt[5]~241COUT1_269 Mega_cnt[6]~237 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.652 ns Mega_cnt\[11\]~217 6 COMB LC_X31_Y15_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.652 ns; Loc. = LC_X31_Y15_N4; Fanout = 6; COMB Node = 'Mega_cnt\[11\]~217'" { } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.136 ns" { Mega_cnt[6]~237 Mega_cnt[11]~217 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.860 ns Mega_cnt\[16\]~197 7 COMB LC_X31_Y15_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 1.860 ns; Loc. = LC_X31_Y15_N9; Fanout = 6; COMB Node = 'Mega_cnt\[16\]~197'" { } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.208 ns" { Mega_cnt[11]~217 Mega_cnt[16]~197 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.996 ns Mega_cnt\[21\]~177 8 COMB LC_X31_Y14_N4 2 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 1.996 ns; Loc. = LC_X31_Y14_N4; Fanout = 2; COMB Node = 'Mega_cnt\[21\]~177'" { } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.136 ns" { Mega_cnt[16]~197 Mega_cnt[21]~177 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.835 ns Mega_cnt\[22\] 9 REG LC_X31_Y14_N5 3 " "Info: 9: + IC(0.000 ns) + CELL(0.839 ns) = 2.835 ns; Loc. = LC_X31_Y14_N5; Fanout = 3; REG Node = 'Mega_cnt\[22\]'" { } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.839 ns" { Mega_cnt[21]~177 Mega_cnt[22] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.312 ns 81.55 % " "Info: Total cell delay = 2.312 ns ( 81.55 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.523 ns 18.45 % " "Info: Total interconnect delay = 0.523 ns ( 18.45 % )" { } { } 0} } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "2.835 ns" { Mega_cnt[3] Mega_cnt[3]~249COUT1_267 Mega_cnt[4]~245COUT1_268 Mega_cnt[5]~241COUT1_269 Mega_cnt[6]~237 Mega_cnt[11]~217 Mega_cnt[16]~197 Mega_cnt[21]~177 Mega_cnt[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.835 ns" { Mega_cnt[3] Mega_cnt[3]~249COUT1_267 Mega_cnt[4]~245COUT1_268 Mega_cnt[5]~241COUT1_269 Mega_cnt[6]~237 Mega_cnt[11]~217 Mega_cnt[16]~197 Mega_cnt[21]~177 Mega_cnt[22] } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.839ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.019 ns - Smallest " "Info: - Smallest clock skew is -0.019 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MMCLK destination 3.944 ns + Shortest register " "Info: + Shortest clock path from clock \"MMCLK\" to destination register is 3.944 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MMCLK 1 CLK PIN_153 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 25; CLK Node = 'MMCLK'" { } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { MMCLK } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 31 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.764 ns) + CELL(0.711 ns) 3.944 ns Mega_cnt\[22\] 2 REG LC_X31_Y14_N5 3 " "Info: 2: + IC(1.764 ns) + CELL(0.711 ns) = 3.944 ns; Loc. = LC_X31_Y14_N5; Fanout = 3; REG Node = 'Mega_cnt\[22\]'" { } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "2.475 ns" { MMCLK Mega_cnt[22] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 55.27 % " "Info: Total cell delay = 2.180 ns ( 55.27 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.764 ns 44.73 % " "Info: Total interconnect delay = 1.764 ns ( 44.73 % )" { } { } 0} } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "3.944 ns" { MMCLK Mega_cnt[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.944 ns" { MMCLK MMCLK~out0 Mega_cnt[22] } { 0.000ns 0.000ns 1.764ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MMCLK source 3.963 ns - Longest register " "Info: - Longest clock path from clock \"MMCLK\" to source register is 3.963 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MMCLK 1 CLK PIN_153 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 25; CLK Node = 'MMCLK'" { } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { MMCLK } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 31 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.783 ns) + CELL(0.711 ns) 3.963 ns Mega_cnt\[3\] 2 REG LC_X31_Y16_N6 3 " "Info: 2: + IC(1.783 ns) + CELL(0.711 ns) = 3.963 ns; Loc. = LC_X31_Y16_N6; Fanout = 3; REG Node = 'Mega_cnt\[3\]'" { } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "2.494 ns" { MMCLK Mega_cnt[3] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 55.01 % " "Info: Total cell delay = 2.180 ns ( 55.01 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.783 ns 44.99 % " "Info: Total interconnect delay = 1.783 ns ( 44.99 % )" { } { } 0} } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "3.963 ns" { MMCLK Mega_cnt[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.963 ns" { MMCLK MMCLK~out0 Mega_cnt[3] } { 0.000ns 0.000ns 1.783ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "3.944 ns" { MMCLK Mega_cnt[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.944 ns" { MMCLK MMCLK~out0 Mega_cnt[22] } { 0.000ns 0.000ns 1.764ns } { 0.000ns 1.469ns 0.711ns } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "3.963 ns" { MMCLK Mega_cnt[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.963 ns" { MMCLK MMCLK~out0 Mega_cnt[3] } { 0.000ns 0.000ns 1.783ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0} } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "2.835 ns" { Mega_cnt[3] Mega_cnt[3]~249COUT1_267 Mega_cnt[4]~245COUT1_268 Mega_cnt[5]~241COUT1_269 Mega_cnt[6]~237 Mega_cnt[11]~217 Mega_cnt[16]~197 Mega_cnt[21]~177 Mega_cnt[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.835 ns" { Mega_cnt[3] Mega_cnt[3]~249COUT1_267 Mega_cnt[4]~245COUT1_268 Mega_cnt[5]~241COUT1_269 Mega_cnt[6]~237 Mega_cnt[11]~217 Mega_cnt[16]~197 Mega_cnt[21]~177 Mega_cnt[22] } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.839ns } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "3.944 ns" { MMCLK Mega_cnt[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.944 ns" { MMCLK MMCLK~out0 Mega_cnt[22] } { 0.000ns 0.000ns 1.764ns } { 0.000ns 1.469ns 0.711ns } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "3.963 ns" { MMCLK Mega_cnt[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.963 ns" { MMCLK MMCLK~out0 Mega_cnt[3] } { 0.000ns 0.000ns 1.783ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { Mega_cnt[22] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { Mega_cnt[22] } { } { } } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } } } 0}
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