myfx2.fit.qmsg

FPGA与USB通信的测试代码

{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "48 " "Warning: The following 48 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPD\[3\] a permanently enabled " "Info: Pin GPD\[3\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 23 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GPD\[3\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { GPD[3] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { GPD[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPD\[4\] a permanently enabled " "Info: Pin GPD\[4\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 23 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GPD\[4\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { GPD[4] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { GPD[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPD\[5\] a permanently enabled " "Info: Pin GPD\[5\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 23 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GPD\[5\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { GPD[5] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { GPD[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPD\[6\] a permanently enabled " "Info: Pin GPD\[6\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 23 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GPD\[6\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { GPD[6] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { GPD[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPD\[7\] a permanently enabled " "Info: Pin GPD\[7\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 23 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GPD\[7\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { GPD[7] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { GPD[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPD\[8\] a permanently enabled " "Info: Pin GPD\[8\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 23 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GPD\[8\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { GPD[8] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { GPD[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPD\[9\] a permanently enabled " "Info: Pin GPD\[9\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 23 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GPD\[9\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { GPD[9] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { GPD[9] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPD\[10\] a permanently enabled " "Info: Pin GPD\[10\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 23 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GPD\[10\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { GPD[10] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { GPD[10] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPD\[11\] a permanently enabled " "Info: Pin GPD\[11\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 23 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GPD\[11\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { GPD[11] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { GPD[11] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPD\[12\] a permanently enabled " "Info: Pin GPD\[12\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 23 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GPD\[12\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { GPD[12] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { GPD[12] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPD\[13\] a permanently enabled " "Info: Pin GPD\[13\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 23 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GPD\[13\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { GPD[13] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { GPD[13] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPD\[14\] a permanently enabled " "Info: Pin GPD\[14\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 23 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GPD\[14\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { GPD[14] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { GPD[14] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPD\[15\] a permanently enabled " "Info: Pin GPD\[15\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 23 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GPD\[15\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { GPD[15] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { GPD[15] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[0\] a permanently enabled " "Info: Pin RAMAD\[0\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[0\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[0] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[1\] a permanently enabled " "Info: Pin RAMAD\[1\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[1\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[1] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[2\] a permanently enabled " "Info: Pin RAMAD\[2\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[2\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[2] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[3\] a permanently enabled " "Info: Pin RAMAD\[3\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[3\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[3] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[4\] a permanently enabled " "Info: Pin RAMAD\[4\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[4\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[4] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[5\] a permanently enabled " "Info: Pin RAMAD\[5\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[5\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[5] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[6\] a permanently enabled " "Info: Pin RAMAD\[6\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[6\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[6] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[7\] a permanently enabled " "Info: Pin RAMAD\[7\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[7\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[7] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[8\] a permanently enabled " "Info: Pin RAMAD\[8\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[8\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[8] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[9\] a permanently enabled " "Info: Pin RAMAD\[9\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[9\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[9] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[9] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[10\] a permanently enabled " "Info: Pin RAMAD\[10\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[10\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[10] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[10] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[11\] a permanently enabled " "Info: Pin RAMAD\[11\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[11\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[11] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[11] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[12\] a permanently enabled " "Info: Pin RAMAD\[12\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[12\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[12] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[12] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[13\] a permanently enabled " "Info: Pin RAMAD\[13\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[13\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[13] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[13] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[14\] a permanently enabled " "Info: Pin RAMAD\[14\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[14\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[14] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[14] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMAD\[15\] a permanently enabled " "Info: Pin RAMAD\[15\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 15 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMAD\[15\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMAD[15] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMAD[15] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMBD\[0\] a permanently enabled " "Info: Pin RAMBD\[0\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 16 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMBD\[0\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMBD[0] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMBD[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMBD\[1\] a permanently enabled " "Info: Pin RAMBD\[1\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 16 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMBD\[1\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMBD[1] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMBD[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMBD\[2\] a permanently enabled " "Info: Pin RAMBD\[2\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 16 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMBD\[2\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMBD[2] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMBD[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMBD\[3\] a permanently enabled " "Info: Pin RAMBD\[3\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 16 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMBD\[3\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { RAMBD[3] } "NODE_NAME" } "" } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.fld" "" "" { RAMBD[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RAMBD\[4\] a permanently enabled " "Info: Pin RAMBD\[4\] has a permanently enabled output enable" {  } { { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 16 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RAMBD\[4\]" } } } } { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/