myfx2.fit.qmsg

FPGA与USB通信的测试代码

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.849 ns register register " "Info: Estimated most critical path is register to register delay of 2.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Mega_cnt\[2\] 1 REG LAB_X31_Y16 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X31_Y16; Fanout = 3; REG Node = 'Mega_cnt\[2\]'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "" { Mega_cnt[2] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.470 ns) + CELL(0.575 ns) 1.045 ns Mega_cnt\[2\]~253COUT1_266 2 COMB LAB_X31_Y16 2 " "Info: 2: + IC(0.470 ns) + CELL(0.575 ns) = 1.045 ns; Loc. = LAB_X31_Y16; Fanout = 2; COMB Node = 'Mega_cnt\[2\]~253COUT1_266'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "1.045 ns" { Mega_cnt[2] Mega_cnt[2]~253COUT1_266 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.125 ns Mega_cnt\[3\]~249COUT1_267 3 COMB LAB_X31_Y16 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.125 ns; Loc. = LAB_X31_Y16; Fanout = 2; COMB Node = 'Mega_cnt\[3\]~249COUT1_267'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.080 ns" { Mega_cnt[2]~253COUT1_266 Mega_cnt[3]~249COUT1_267 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.205 ns Mega_cnt\[4\]~245COUT1_268 4 COMB LAB_X31_Y16 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.205 ns; Loc. = LAB_X31_Y16; Fanout = 2; COMB Node = 'Mega_cnt\[4\]~245COUT1_268'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.080 ns" { Mega_cnt[3]~249COUT1_267 Mega_cnt[4]~245COUT1_268 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.285 ns Mega_cnt\[5\]~241COUT1_269 5 COMB LAB_X31_Y16 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.285 ns; Loc. = LAB_X31_Y16; Fanout = 2; COMB Node = 'Mega_cnt\[5\]~241COUT1_269'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.080 ns" { Mega_cnt[4]~245COUT1_268 Mega_cnt[5]~241COUT1_269 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.543 ns Mega_cnt\[6\]~237 6 COMB LAB_X31_Y16 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.543 ns; Loc. = LAB_X31_Y16; Fanout = 6; COMB Node = 'Mega_cnt\[6\]~237'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.258 ns" { Mega_cnt[5]~241COUT1_269 Mega_cnt[6]~237 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.679 ns Mega_cnt\[11\]~217 7 COMB LAB_X31_Y15 6 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.679 ns; Loc. = LAB_X31_Y15; Fanout = 6; COMB Node = 'Mega_cnt\[11\]~217'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.136 ns" { Mega_cnt[6]~237 Mega_cnt[11]~217 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.815 ns Mega_cnt\[16\]~197 8 COMB LAB_X31_Y15 6 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 1.815 ns; Loc. = LAB_X31_Y15; Fanout = 6; COMB Node = 'Mega_cnt\[16\]~197'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.136 ns" { Mega_cnt[11]~217 Mega_cnt[16]~197 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.951 ns Mega_cnt\[21\]~177 9 COMB LAB_X31_Y14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 1.951 ns; Loc. = LAB_X31_Y14; Fanout = 2; COMB Node = 'Mega_cnt\[21\]~177'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.136 ns" { Mega_cnt[16]~197 Mega_cnt[21]~177 } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 2.849 ns Mega_cnt\[23\] 10 REG LAB_X31_Y14 2 " "Info: 10: + IC(0.000 ns) + CELL(0.898 ns) = 2.849 ns; Loc. = LAB_X31_Y14; Fanout = 2; REG Node = 'Mega_cnt\[23\]'" {  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "0.898 ns" { Mega_cnt[21]~177 Mega_cnt[23] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/MYFX2.v" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.379 ns 83.50 % " "Info: Total cell delay = 2.379 ns ( 83.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.470 ns 16.50 % " "Info: Total interconnect delay = 0.470 ns ( 16.50 % )" {  } {  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板/测试程序源代码（包括VC工程文件及Firmware）/USB2.0+FPGA_EXAMPLES/KEY_LED/" "" "2.849 ns" { Mega_cnt[2] Mega_cnt[2]~253COUT1_266 Mega_cnt[3]~249COUT1_267 Mega_cnt[4]~245COUT1_268 Mega_cnt[5]~241COUT1_269 Mega_cnt[6]~237 Mega_cnt[11]~217 Mega_cnt[16]~197 Mega_cnt[21]~177 Mega_cnt[23] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}