myfx2.tan.rpt

FPGA与USB通信的测试代码

+---------------+-------------+-----------+--------+-----+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Nov 03 08:53:21 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off MYFX2 -c MYFX2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "MMCLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "Mega_cnt[23]" as buffer
Info: Clock "MMCLK" Internal fmax is restricted to 275.03 MHz between source register "Mega_cnt[3]" and destination register "Mega_cnt[22]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.835 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y16_N6; Fanout = 3; REG Node = 'Mega_cnt[3]'
            Info: 2: + IC(0.523 ns) + CELL(0.575 ns) = 1.098 ns; Loc. = LC_X31_Y16_N6; Fanout = 2; COMB Node = 'Mega_cnt[3]~249COUT1_267'
            Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.178 ns; Loc. = LC_X31_Y16_N7; Fanout = 2; COMB Node = 'Mega_cnt[4]~245COUT1_268'
            Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.258 ns; Loc. = LC_X31_Y16_N8; Fanout = 2; COMB Node = 'Mega_cnt[5]~241COUT1_269'
            Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.516 ns; Loc. = LC_X31_Y16_N9; Fanout = 6; COMB Node = 'Mega_cnt[6]~237'
            Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.652 ns; Loc. = LC_X31_Y15_N4; Fanout = 6; COMB Node = 'Mega_cnt[11]~217'
            Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 1.860 ns; Loc. = LC_X31_Y15_N9; Fanout = 6; COMB Node = 'Mega_cnt[16]~197'
            Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 1.996 ns; Loc. = LC_X31_Y14_N4; Fanout = 2; COMB Node = 'Mega_cnt[21]~177'
            Info: 9: + IC(0.000 ns) + CELL(0.839 ns) = 2.835 ns; Loc. = LC_X31_Y14_N5; Fanout = 3; REG Node = 'Mega_cnt[22]'
            Info: Total cell delay = 2.312 ns ( 81.55 % )
            Info: Total interconnect delay = 0.523 ns ( 18.45 % )
        Info: - Smallest clock skew is -0.019 ns
            Info: + Shortest clock path from clock "MMCLK" to destination register is 3.944 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 25; CLK Node = 'MMCLK'
                Info: 2: + IC(1.764 ns) + CELL(0.711 ns) = 3.944 ns; Loc. = LC_X31_Y14_N5; Fanout = 3; REG Node = 'Mega_cnt[22]'
                Info: Total cell delay = 2.180 ns ( 55.27 % )
                Info: Total interconnect delay = 1.764 ns ( 44.73 % )
            Info: - Longest clock path from clock "MMCLK" to source register is 3.963 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 25; CLK Node = 'MMCLK'
                Info: 2: + IC(1.783 ns) + CELL(0.711 ns) = 3.963 ns; Loc. = LC_X31_Y16_N6; Fanout = 3; REG Node = 'Mega_cnt[3]'
                Info: Total cell delay = 2.180 ns ( 55.01 % )
                Info: Total interconnect delay = 1.783 ns ( 44.99 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "LDT" (data pin = "nRESET", clock pin = "MMCLK") is -1.970 ns
    Info: + Longest pin to register delay is 3.450 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_131; Fanout = 25; PIN Node = 'nRESET'
        Info: 2: + IC(1.114 ns) + CELL(0.867 ns) = 3.450 ns; Loc. = LC_X31_Y14_N9; Fanout = 2; REG Node = 'LDT'
        Info: Total cell delay = 2.336 ns ( 67.71 % )
        Info: Total interconnect delay = 1.114 ns ( 32.29 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "MMCLK" to destination register is 5.457 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 25; CLK Node = 'MMCLK'
        Info: 2: + IC(1.764 ns) + CELL(0.935 ns) = 4.168 ns; Loc. = LC_X31_Y14_N6; Fanout = 2; REG Node = 'Mega_cnt[23]'
        Info: 3: + IC(0.578 ns) + CELL(0.711 ns) = 5.457 ns; Loc. = LC_X31_Y14_N9; Fanout = 2; REG Node = 'LDT'
        Info: Total cell delay = 3.115 ns ( 57.08 % )
        Info: Total interconnect delay = 2.342 ns ( 42.92 % )
Info: tco from clock "MMCLK" to destination pin "LED[3]" through register "LDT" is 10.080 ns
    Info: + Longest clock path from clock "MMCLK" to source register is 5.457 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 25; CLK Node = 'MMCLK'
        Info: 2: + IC(1.764 ns) + CELL(0.935 ns) = 4.168 ns; Loc. = LC_X31_Y14_N6; Fanout = 2; REG Node = 'Mega_cnt[23]'
        Info: 3: + IC(0.578 ns) + CELL(0.711 ns) = 5.457 ns; Loc. = LC_X31_Y14_N9; Fanout = 2; REG Node = 'LDT'
        Info: Total cell delay = 3.115 ns ( 57.08 % )
        Info: Total interconnect delay = 2.342 ns ( 42.92 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.399 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y14_N9; Fanout = 2; REG Node = 'LDT'
        Info: 2: + IC(2.275 ns) + CELL(2.124 ns) = 4.399 ns; Loc. = PIN_180; Fanout = 0; PIN Node = 'LED[3]'
        Info: Total cell delay = 2.124 ns ( 48.28 % )
        Info: Total interconnect delay = 2.275 ns ( 51.72 % )
Info: Longest tpd from source pin "PA[0]" to destination pin "LED[0]" is 13.088 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_44; Fanout = 1; PIN Node = 'PA[0]'
    Info: 2: + IC(9.511 ns) + CELL(2.108 ns) = 13.088 ns; Loc. = PIN_183; Fanout = 0; PIN Node = 'LED[0]'
    Info: Total cell delay = 3.577 ns ( 27.33 % )
    Info: Total interconnect delay = 9.511 ns ( 72.67 % )
Info: th for register "LDT" (data pin = "nRESET", clock pin = "MMCLK") is 2.022 ns
    Info: + Longest clock path from clock "MMCLK" to destination register is 5.457 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 25; CLK Node = 'MMCLK'
        Info: 2: + IC(1.764 ns) + CELL(0.935 ns) = 4.168 ns; Loc. = LC_X31_Y14_N6; Fanout = 2; REG Node = 'Mega_cnt[23]'
        Info: 3: + IC(0.578 ns) + CELL(0.711 ns) = 5.457 ns; Loc. = LC_X31_Y14_N9; Fanout = 2; REG Node = 'LDT'
        Info: Total cell delay = 3.115 ns ( 57.08 % )
        Info: Total interconnect delay = 2.342 ns ( 42.92 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 3.450 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_131; Fanout = 25; PIN Node = 'nRESET'
        Info: 2: + IC(1.