myfx2.tan.rpt

FPGA与USB通信的测试代码

Timing Analyzer report for MYFX2
Mon Sep 18 20:41:46 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                    ;
+------------------------------+-------+---------------+-------------+-------+--------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From  ; To     ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------+--------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 13.402 ns   ; PA[3] ; LED[3] ;            ;          ; 0            ;
; Total number of failed paths ;       ;               ;             ;       ;        ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+-------+--------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------+
; tpd                                                           ;
+-------+-------------------+-----------------+--------+--------+
; Slack ; Required P2P Time ; Actual P2P Time ; From   ; To     ;
+-------+-------------------+-----------------+--------+--------+
; N/A   ; None              ; 13.402 ns       ; PA[3]  ; LED[3] ;
; N/A   ; None              ; 13.088 ns       ; PA[0]  ; LED[0] ;
; N/A   ; None              ; 13.002 ns       ; PA[1]  ; LED[1] ;
; N/A   ; None              ; 12.927 ns       ; PA[2]  ; LED[2] ;
; N/A   ; None              ; 12.770 ns       ; KEY[2] ; PA[6]  ;
; N/A   ; None              ; 12.461 ns       ; KEY[1] ; PA[5]  ;
; N/A   ; None              ; 12.392 ns       ; KEY[0] ; PA[4]  ;
; N/A   ; None              ; 5.957 ns        ; MMCLK  ; USBCLK ;
+-------+-------------------+-----------------+--------+--------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Sep 18 20:41:45 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off MYFX2 -c MYFX2 --timing_analysis_only
Info: Longest tpd from source pin "PA[3]" to destination pin "LED[3]" is 13.402 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_41; Fanout = 1; PIN Node = 'PA[3]'
    Info: 2: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = IOC_X0_Y7_N0; Fanout = 1; COMB Node = 'PA[3]~0'
    Info: 3: + IC(9.809 ns) + CELL(2.124 ns) = 13.402 ns; Loc. = PIN_180; Fanout = 0; PIN Node = 'LED[3]'
    Info: Total cell delay = 3.593 ns ( 26.81 % )
    Info: Total interconnect delay = 9.809 ns ( 73.19 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Sep 18 20:41:46 2006
    Info: Elapsed time: 00:00:01