myfx2.map.rpt

FPGA与USB通信的测试代码

+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/曹雄恒/桌面/MYFPGAT2/MYFX2.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Sep 20 21:28:40 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MYFX2 -c MYFX2
Warning: (10273) Verilog HDL warning at MYFX2.v(80): extended using "x" or "z"
Warning: (10273) Verilog HDL warning at MYFX2.v(81): extended using "x" or "z"
Info: Found 1 design units, including 1 entities, in source file MYFX2.v
    Info: Found entity 1: MYFX2
Info: Elaborating entity "MYFX2" for the top level hierarchy
Warning: Verilog HDL assignment warning at MYFX2.v(63): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at MYFX2.v(64): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at MYFX2.v(65): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL Always Construct warning at MYFX2.v(74): variable "GPD" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at MYFX2.v(75): variable "RAMBD" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: (10270) Verilog HDL statement warning at MYFX2.v(72): incomplete Case Statement has no default case item
Info: Verilog HDL Case Statement information at MYFX2.v(72): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement
Warning: Verilog HDL Always Construct warning at MYFX2.v(70): variable "DREG" may not be assigned a new value in every possible path through the Always Construct.  Variable "DREG" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL assignment warning at MYFX2.v(80): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at MYFX2.v(81): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at MYFX2.v(84): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at MYFX2.v(85): truncated value with size 32 to match size of target (1)
Warning: Output port "RAMAA[17]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[16]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[15]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[14]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[13]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[12]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[11]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[10]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[9]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[8]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[7]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[6]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[5]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[4]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[3]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[2]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[1]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAA[0]" at MYFX2.v(13) has no driver
Warning: Output port "RAMAUB" at MYFX2.v(18) has no driver
Warning: Output port "RAMALB" at MYFX2.v(18) has no driver
Warning: Output port "RAMAWE" at MYFX2.v(18) has no driver
Warning: Output port "RAMACE" at MYFX2.v(18) has no driver
Warning: Output port "RAMAOE" at MYFX2.v(18) has no driver
Warning: Output port "LED[3]" at MYFX2.v(36) has no driver
Warning: Output port "LED[2]" at MYFX2.v(36) has no driver
Warning: Output port "LED[1]" at MYFX2.v(36) has no driver
Warning: Output port "LED[0]" at MYFX2.v(36) has no driver
Warning: Latch DREG[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[8] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[9] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[10] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[11] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[12] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[13] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[14] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Latch DREG[15] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CTL[5]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "LED[0]" stuck at GND
    Warning: Pin "LED[1]" stuck at GND
    Warning: Pin "LED[2]" stuck at GND
    Warning: Pin "LED[3]" stuck at GND
    Warning: Pin "RAMAA[0]" stuck at GND
    Warning: Pin "RAMAA[1]" stuck at GND
    Warning: Pin "RAMAA[2]" stuck at GND
    Warning: Pin "RAMAA[3]" stuck at GND
    Warning: Pin "RAMAA[4]" stuck at GND
    Warning: Pin "RAMAA[5]" stuck at GND
    Warning: Pin "RAMAA[6]" stuck at GND
    Warning: Pin "RAMAA[7]" stuck at GND
    Warning: Pin "RAMAA[8]" stuck at GND
    Warning: Pin "RAMAA[9]" stuck at GND
    Warning: Pin "RAMAA[10]" stuck at GND
    Warning: Pin "RAMAA[11]" stuck at GND
    Warning: Pin "RAMAA[12]" stuck at GND
    Warning: Pin "RAMAA[13]" stuck at GND
    Warning: Pin "RAMAA[14]" stuck at GND
    Warning: Pin "RAMAA[15]" stuck at GND
    Warning: Pin "RAMAA[16]" stuck at GND
    Warning: Pin "RAMAA[17]" stuck at GND
    Warning: Pin "RAMAUB" stuck at GND
    Warning: Pin "RAMALB" stuck at GND
    Warning: Pin "RAMAWE" stuck at GND
    Warning: Pin "RAMACE" stuck at GND
    Warning: Pin "RAMAOE" stuck at GND
    Warning: Pin "RAMBA[15]" stuck at GND
    Warning: Pin "RAMBA[16]" stuck at GND
    Warning: Pin "RAMBA[17]" stuck at GND
    Warning: Pin "RAMBUB" stuck at VCC
    Warning: Pin "RAMBLB" stuck at GND
Warning: Design contains 24 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "nRESET"
    Warning: No output dependent on input pin "PA[6]"
    Warning: No output dependent on input pin "PA[7]"
    Warning: No output dependent on input pin "CTL[0]"
    Warning: No output dependent on input pin "CTL[1]"
    Warning: No output dependent on input pin "CTL[2]"
    Warning: No output dependent on input pin "RDY[0]"
    Warning: No output dependent on input pin "RDY[1]"
    Warning: No output dependent on input pin "RDY[2]"
    Warning: No output dependent on input pin "RDY[3]"
    Warning: No output dependent on input pin "RDY[4]"
    Warning: No output dependent on input pin "RDY[5]"
    Warning: No output dependent on input pin "USER[0]"
    Warning: No output dependent on input pin "USER[1]"
    Warning: No output dependent on input pin "USER[2]"
    Warning: No output dependent on input pin "USER[3]"
    Warning: No output dependent on input pin "USER[4]"
    Warning: No output dependent on input pin "USER[5]"
    Warning: No output dependent on input pin "IFCLK"
    Warning: No output dependent on input pin "CLKOUT"
    Warning: No output dependent on input pin "nINT5"
    Warning: No output dependent on input pin "KEY[0]"
    Warning: No output dependent on input pin "KEY[1]"
    Warning: No output dependent on input pin "KEY[2]"
Info: Implemented 175 device resources after synthesis - the final resource count might be different
    Info: Implemented 43 input pins
    Info: Implemented 51 output pins
    Info: Implemented 48 bidirectional pins
    Info: Implemented 33 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 130 warnings
    Info: Processing ended: Wed Sep 20 21:28:41 2006
    Info: Elapsed time: 00:00:02