myfx2.v

FPGA与USB通信的测试代码

module MYFX2 (
              nRESET,	PA, GPD,GPA , CTL,RDY,USER, // Inputs from FX2
              IFCLK,CLKOUT, nINT5,// Inputs from FX2

			   USBCLK,		// Output to FX2		  
		       MMCLK,       //from cytal
     		   LED,		    // LED indicator
               KEY,
               RAMAA,RAMAD,RAMAUB,RAMALB,RAMAWE,RAMACE,RAMAOE,
               RAMBA,RAMBD,RAMBUB,RAMBLB,RAMBWE,RAMBCE,RAMBOE
              );
//////////////////////////////////
output [17:0]RAMAA;
output [17:0]RAMBA;
inout  [15:0]RAMAD;
wire   [15:0]RAMBD;
inout  [15:0]RAMBD;
output RAMAUB,RAMALB,RAMAWE,RAMACE,RAMAOE;
output RAMBUB,RAMBLB,RAMBWE,RAMBCE,RAMBOE;
////////////////////////////////////////////
input nRESET;
///////////////////////////////////
input [7:0]PA;
inout [15:0]GPD;
wire  [15:0]GPD;
input [8:0]GPA;
input [5:0]CTL;
input [5:0]RDY;
input [5:0]USER;
input IFCLK,CLKOUT, nINT5;
//////////////////////////////////
reg [15:0]DREG;
input MMCLK;
input [2:0]KEY;

output  [3:0]LED;
//reg [3:0]LED;


output  USBCLK;


assign USBCLK=MMCLK;


////////////////////////////////////////
assign RAMBA[0]=GPA[0];
assign RAMBA[1]=GPA[1];
assign RAMBA[2]=GPA[2];
assign RAMBA[3]=GPA[3];
assign RAMBA[4]=GPA[4];
assign RAMBA[5]=GPA[5];
assign RAMBA[6]=GPA[6];
assign RAMBA[7]=GPA[7];
assign RAMBA[8]=GPA[8];
assign RAMBA[9]=PA[0];
assign RAMBA[10]=PA[1];
assign RAMBA[11]=PA[2];
assign RAMBA[12]=PA[3];
assign RAMBA[13]=PA[4];
assign RAMBA[14]=PA[5];

assign RAMBA[15]=0;
assign RAMBA[16]=0;
assign RAMBA[17]=0;



////////////////////////////////////////
always @(negedge RAMBWE or negedge RAMBOE)
begin
case ({RAMBWE,RAMBOE})
  
      2'b01:  DREG=GPD;
      2'b10:  DREG=RAMBD; 
   
endcase
end

assign GPD=RAMBWE?DREG:'hzz;
assign RAMBD=RAMBOE?DREG:'hzz;

///////////////////////////////////////////
assign RAMBUB=1;
assign RAMBLB=0;
assign RAMBWE=CTL[5];
assign RAMBCE=CTL[3];
assign RAMBOE=CTL[4];
////////////////////////////

												
endmodule