📄 usb.plg
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<h1>Build Log</h1>
<h3>
--------------------Configuration: USB - Win32 Debug--------------------
</h3>
<h3>Command Lines</h3>
Creating temporary file "C:\DOCUME~1\ADMINI~1.81C\LOCALS~1\Temp\RSPD0.tmp" with contents
[
/nologo /MDd /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_WINDOWS" /D "_AFXDLL" /D "_MBCS" /FR"Debug/" /Fp"Debug/USB.pch" /Yc"stdafx.h" /Fo"Debug/" /Fd"Debug/" /FD /GZ /c
"E:\我的文档\杂合资料\嵌入式相关资料\YCL-USB2.0-FPGA开发板\测试程序源代码（包括VC工程文件及Firmware,Verilog代码）\USB2.0+FPGA_EXAMPLES\SLAVE FIFO8测试\应用程序\StdAfx.cpp"
]
Creating command line "cl.exe @C:\DOCUME~1\ADMINI~1.81C\LOCALS~1\Temp\RSPD0.tmp"
Creating temporary file "C:\DOCUME~1\ADMINI~1.81C\LOCALS~1\Temp\RSPD1.tmp" with contents
[
/nologo /MDd /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_WINDOWS" /D "_AFXDLL" /D "_MBCS" /FR"Debug/" /Fp"Debug/USB.pch" /Yu"stdafx.h" /Fo"Debug/" /Fd"Debug/" /FD /GZ /c
"E:\我的文档\杂合资料\嵌入式相关资料\YCL-USB2.0-FPGA开发板\测试程序源代码（包括VC工程文件及Firmware,Verilog代码）\USB2.0+FPGA_EXAMPLES\SLAVE FIFO8测试\应用程序\USB.cpp"
"E:\我的文档\杂合资料\嵌入式相关资料\YCL-USB2.0-FPGA开发板\测试程序源代码（包括VC工程文件及Firmware,Verilog代码）\USB2.0+FPGA_EXAMPLES\SLAVE FIFO8测试\应用程序\USBDlg.cpp"
]
Creating command line "cl.exe @C:\DOCUME~1\ADMINI~1.81C\LOCALS~1\Temp\RSPD1.tmp"
<h3>Output Window</h3>
Compiling...
StdAfx.cpp
Compiling...
USB.cpp
USBDlg.cpp
E:\我的文档\杂合资料\嵌入式相关资料\YCL-USB2.0-FPGA开发板\测试程序源代码（包括VC工程文件及Firmware,Verilog代码）\USB2.0+FPGA_EXAMPLES\SLAVE FIFO8测试\应用程序\USBDlg.cpp(567) : warning C4018: '<' : signed/unsigned mismatch
Generating Code...
Creating command line "link.exe /nologo /subsystem:windows /incremental:yes /pdb:"Debug/USB.pdb" /debug /machine:I386 /out:"Debug/USB.exe" /pdbtype:sept ".\Debug\StdAfx.obj" ".\Debug\USB.obj" ".\Debug\USBDlg.obj" ".\Debug\USB.res" "
<h3>Output Window</h3>
Linking...
Creating command line "bscmake.exe /nologo /o"Debug/USB.bsc" ".\Debug\StdAfx.sbr" ".\Debug\USB.sbr" ".\Debug\USBDlg.sbr""
Creating browse info file...
<h3>Output Window</h3>
<h3>Results</h3>
USB.exe - 0 error(s), 1 warning(s)
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