myfx2.map.eqn

FPGA与USB通信的测试代码

-- Copyright (C) 1991-2005 Altera Corporation
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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--A1L471Q is RDY[1]~reg0
--operation mode is normal

A1L471Q_lut_out = STATE.WRITE_1;
A1L471Q = DFFEAS(A1L471Q_lut_out, CLK_2, KEY[0], , , , , , );


--STATE.WRITE_1 is STATE.WRITE_1
--operation mode is normal

STATE.WRITE_1_lut_out = A1L471Q # !STATE.IDLE;
STATE.WRITE_1 = DFFEAS(STATE.WRITE_1_lut_out, CLK_2, KEY[0], , , , , , );


--CLK_2 is CLK_2
--operation mode is normal

CLK_2_lut_out = !CLK_2;
CLK_2 = DFFEAS(CLK_2_lut_out, MMCLK, VCC, , , , , , );


--STATE.IDLE is STATE.IDLE
--operation mode is normal

STATE.IDLE_lut_out = VCC;
STATE.IDLE = DFFEAS(STATE.IDLE_lut_out, CLK_2, KEY[0], , , , , , );


--DREG[0] is DREG[0]
--operation mode is arithmetic

DREG[0]_lut_out = !DREG[0];
DREG[0] = DFFEAS(DREG[0]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L21 is DREG[0]~129
--operation mode is arithmetic

A1L21 = CARRY(DREG[0]);


--DREG[1] is DREG[1]
--operation mode is arithmetic

DREG[1]_carry_eqn = A1L21;
DREG[1]_lut_out = DREG[1] $ (DREG[1]_carry_eqn);
DREG[1] = DFFEAS(DREG[1]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L41 is DREG[1]~133
--operation mode is arithmetic

A1L41 = CARRY(!A1L21 # !DREG[1]);


--DREG[2] is DREG[2]
--operation mode is arithmetic

DREG[2]_carry_eqn = A1L41;
DREG[2]_lut_out = DREG[2] $ (!DREG[2]_carry_eqn);
DREG[2] = DFFEAS(DREG[2]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L61 is DREG[2]~137
--operation mode is arithmetic

A1L61 = CARRY(DREG[2] & (!A1L41));


--DREG[3] is DREG[3]
--operation mode is arithmetic

DREG[3]_carry_eqn = A1L61;
DREG[3]_lut_out = DREG[3] $ (DREG[3]_carry_eqn);
DREG[3] = DFFEAS(DREG[3]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L81 is DREG[3]~141
--operation mode is arithmetic

A1L81 = CARRY(!A1L61 # !DREG[3]);


--DREG[4] is DREG[4]
--operation mode is arithmetic

DREG[4]_carry_eqn = A1L81;
DREG[4]_lut_out = DREG[4] $ (!DREG[4]_carry_eqn);
DREG[4] = DFFEAS(DREG[4]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L02 is DREG[4]~145
--operation mode is arithmetic

A1L02 = CARRY(DREG[4] & (!A1L81));


--DREG[5] is DREG[5]
--operation mode is arithmetic

DREG[5]_carry_eqn = A1L02;
DREG[5]_lut_out = DREG[5] $ (DREG[5]_carry_eqn);
DREG[5] = DFFEAS(DREG[5]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L22 is DREG[5]~149
--operation mode is arithmetic

A1L22 = CARRY(!A1L02 # !DREG[5]);


--DREG[6] is DREG[6]
--operation mode is arithmetic

DREG[6]_carry_eqn = A1L22;
DREG[6]_lut_out = DREG[6] $ (!DREG[6]_carry_eqn);
DREG[6] = DFFEAS(DREG[6]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L42 is DREG[6]~153
--operation mode is arithmetic

A1L42 = CARRY(DREG[6] & (!A1L22));


--DREG[7] is DREG[7]
--operation mode is arithmetic

DREG[7]_carry_eqn = A1L42;
DREG[7]_lut_out = DREG[7] $ (DREG[7]_carry_eqn);
DREG[7] = DFFEAS(DREG[7]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L62 is DREG[7]~157
--operation mode is arithmetic

A1L62 = CARRY(!A1L42 # !DREG[7]);


--DREG[8] is DREG[8]
--operation mode is arithmetic

DREG[8]_carry_eqn = A1L62;
DREG[8]_lut_out = DREG[8] $ (!DREG[8]_carry_eqn);
DREG[8] = DFFEAS(DREG[8]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L82 is DREG[8]~161
--operation mode is arithmetic

A1L82 = CARRY(DREG[8] & (!A1L62));


--DREG[9] is DREG[9]
--operation mode is arithmetic

DREG[9]_carry_eqn = A1L82;
DREG[9]_lut_out = DREG[9] $ (DREG[9]_carry_eqn);
DREG[9] = DFFEAS(DREG[9]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L03 is DREG[9]~165
--operation mode is arithmetic

A1L03 = CARRY(!A1L82 # !DREG[9]);


--DREG[10] is DREG[10]
--operation mode is arithmetic

DREG[10]_carry_eqn = A1L03;
DREG[10]_lut_out = DREG[10] $ (!DREG[10]_carry_eqn);
DREG[10] = DFFEAS(DREG[10]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L23 is DREG[10]~169
--operation mode is arithmetic

A1L23 = CARRY(DREG[10] & (!A1L03));


--DREG[11] is DREG[11]
--operation mode is arithmetic

DREG[11]_carry_eqn = A1L23;
DREG[11]_lut_out = DREG[11] $ (DREG[11]_carry_eqn);
DREG[11] = DFFEAS(DREG[11]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L43 is DREG[11]~173
--operation mode is arithmetic

A1L43 = CARRY(!A1L23 # !DREG[11]);


--DREG[12] is DREG[12]
--operation mode is arithmetic

DREG[12]_carry_eqn = A1L43;
DREG[12]_lut_out = DREG[12] $ (!DREG[12]_carry_eqn);
DREG[12] = DFFEAS(DREG[12]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L63 is DREG[12]~177
--operation mode is arithmetic

A1L63 = CARRY(DREG[12] & (!A1L43));


--DREG[13] is DREG[13]
--operation mode is arithmetic

DREG[13]_carry_eqn = A1L63;
DREG[13]_lut_out = DREG[13] $ (DREG[13]_carry_eqn);
DREG[13] = DFFEAS(DREG[13]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L83 is DREG[13]~181
--operation mode is arithmetic

A1L83 = CARRY(!A1L63 # !DREG[13]);


--DREG[14] is DREG[14]
--operation mode is arithmetic

DREG[14]_carry_eqn = A1L83;
DREG[14]_lut_out = DREG[14] $ (!DREG[14]_carry_eqn);
DREG[14] = DFFEAS(DREG[14]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );

--A1L04 is DREG[14]~185
--operation mode is arithmetic

A1L04 = CARRY(DREG[14] & (!A1L83));


--DREG[15] is DREG[15]
--operation mode is normal

DREG[15]_carry_eqn = A1L04;
DREG[15]_lut_out = DREG[15] $ (DREG[15]_carry_eqn);
DREG[15] = DFFEAS(DREG[15]_lut_out, CLK_2, VCC, , STATE.WRITE_1, VCC, !KEY[0], , );


--nRESET is nRESET
--operation mode is input

nRESET = INPUT();


--GPA[0] is GPA[0]
--operation mode is input

GPA[0] = INPUT();


--GPA[1] is GPA[1]
--operation mode is input

GPA[1] = INPUT();


--GPA[2] is GPA[2]
--operation mode is input

GPA[2] = INPUT();


--GPA[3] is GPA[3]
--operation mode is input

GPA[3] = INPUT();


--GPA[4] is GPA[4]
--operation mode is input

GPA[4] = INPUT();


--GPA[5] is GPA[5]
--operation mode is input

GPA[5] = INPUT();


--GPA[6] is GPA[6]
--operation mode is input

GPA[6] = INPUT();


--GPA[7] is GPA[7]
--operation mode is input

GPA[7] = INPUT();


--GPA[8] is GPA[8]
--operation mode is input

GPA[8] = INPUT();


--CTL[0] is CTL[0]
--operation mode is input

CTL[0] = INPUT();


--CTL[1] is CTL[1]
--operation mode is input

CTL[1] = INPUT();


--CTL[2] is CTL[2]
--operation mode is input

CTL[2] = INPUT();


--CTL[3] is CTL[3]
--operation mode is input

CTL[3] = INPUT();


--CTL[4] is CTL[4]
--operation mode is input

CTL[4] = INPUT();


--CTL[5] is CTL[5]
--operation mode is input

CTL[5] = INPUT();


--USER[0] is USER[0]
--operation mode is input

USER[0] = INPUT();


--USER[1] is USER[1]
--operation mode is input

USER[1] = INPUT();


--USER[2] is USER[2]
--operation mode is input

USER[2] = INPUT();


--USER[3] is USER[3]
--operation mode is input

USER[3] = INPUT();


--USER[4] is USER[4]
--operation mode is input

USER[4] = INPUT();


--USER[5] is USER[5]
--operation mode is input

USER[5] = INPUT();


--IFCLK is IFCLK
--operation mode is input

IFCLK = INPUT();


--CLKOUT is CLKOUT
--operation mode is input

CLKOUT = INPUT();


--nINT5 is nINT5
--operation mode is input

nINT5 = INPUT();


--KEY[1] is KEY[1]
--operation mode is input

KEY[1] = INPUT();


--KEY[2] is KEY[2]
--operation mode is input

KEY[2] = INPUT();


--MMCLK is MMCLK
--operation mode is input

MMCLK = INPUT();


--KEY[0] is KEY[0]
--operation mode is input

KEY[0] = INPUT();


--PA[0] is PA[0]
--operation mode is output

PA[0] = OUTPUT(GND);


--PA[1] is PA[1]
--operation mode is output

PA[1] = OUTPUT(GND);


--PA[2] is PA[2]
--operation mode is output

PA[2] = OUTPUT(GND);


--PA[3] is PA[3]
--operation mode is output

PA[3] = OUTPUT(GND);


--PA[4] is PA[4]
--operation mode is output

PA[4] = OUTPUT(GND);


--PA[5] is PA[5]
--operation mode is output

PA[5] = OUTPUT(VCC);


--PA[6] is PA[6]
--operation mode is output

PA[6] = OUTPUT(GND);


--PA[7] is PA[7]
--operation mode is output

PA[7] = OUTPUT(GND);


--RDY[0] is RDY[0]
--operation mode is output

RDY[0] = OUTPUT(VCC);


--RDY[1] is RDY[1]
--operation mode is output

RDY[1] = OUTPUT(!A1L471Q);


--RDY[2] is RDY[2]
--operation mode is output

RDY[2] = OUTPUT(GND);


--RDY[3] is RDY[3]
--operation mode is output

RDY[3] = OUTPUT(GND);


--RDY[4] is RDY[4]
--operation mode is output

RDY[4] = OUTPUT(GND);


--RDY[5] is RDY[5]
--operation mode is output

RDY[5] = OUTPUT(GND);


--USBCLK is USBCLK
--operation mode is output

USBCLK = OUTPUT(MMCLK);


--LED[0] is LED[0]
--operation mode is output

LED[0] = OUTPUT(VCC);


--LED[1] is LED[1]
--operation mode is output

LED[1] = OUTPUT(GND);


--LED[2] is LED[2]
--operation mode is output

LED[2] = OUTPUT(GND);


--LED[3] is LED[3]
--operation mode is output

LED[3] = OUTPUT(GND);


--RAMAA[0] is RAMAA[0]
--operation mode is output

RAMAA[0] = OUTPUT(GND);


--RAMAA[1] is RAMAA[1]
--operation mode is output

RAMAA[1] = OUTPUT(GND);


--RAMAA[2] is RAMAA[2]
--operation mode is output

RAMAA[2] = OUTPUT(GND);


--RAMAA[3] is RAMAA[3]
--operation mode is output

RAMAA[3] = OUTPUT(GND);


--RAMAA[4] is RAMAA[4]