myfx2.tan.rpt

FPGA与USB通信的测试代码

; N/A   ; None         ; 11.827 ns  ; DREG[14]    ; GPD[14] ; MMCLK      ;
; N/A   ; None         ; 11.827 ns  ; DREG[12]    ; GPD[12] ; MMCLK      ;
; N/A   ; None         ; 11.821 ns  ; DREG[15]    ; GPD[15] ; MMCLK      ;
; N/A   ; None         ; 11.807 ns  ; DREG[13]    ; GPD[13] ; MMCLK      ;
; N/A   ; None         ; 11.621 ns  ; RDY[1]~reg0 ; RDY[1]  ; MMCLK      ;
; N/A   ; None         ; 11.451 ns  ; DREG[11]    ; GPD[11] ; MMCLK      ;
; N/A   ; None         ; 11.449 ns  ; DREG[9]     ; GPD[9]  ; MMCLK      ;
; N/A   ; None         ; 11.448 ns  ; DREG[10]    ; GPD[10] ; MMCLK      ;
; N/A   ; None         ; 11.424 ns  ; RDY[1]~reg0 ; GPD[10] ; MMCLK      ;
; N/A   ; None         ; 11.424 ns  ; RDY[1]~reg0 ; GPD[9]  ; MMCLK      ;
; N/A   ; None         ; 11.418 ns  ; RDY[1]~reg0 ; GPD[11] ; MMCLK      ;
; N/A   ; None         ; 11.002 ns  ; DREG[8]     ; GPD[8]  ; MMCLK      ;
; N/A   ; None         ; 10.928 ns  ; RDY[1]~reg0 ; GPD[8]  ; MMCLK      ;
+-------+--------------+------------+-------------+---------+------------+


+--------------------------------------------------------------+
; tpd                                                          ;
+-------+-------------------+-----------------+-------+--------+
; Slack ; Required P2P Time ; Actual P2P Time ; From  ; To     ;
+-------+-------------------+-----------------+-------+--------+
; N/A   ; None              ; 5.957 ns        ; MMCLK ; USBCLK ;
+-------+-------------------+-----------------+-------+--------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Nov 02 19:50:37 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off MYFX2 -c MYFX2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "MMCLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "CLK_2" as buffer
Info: Clock "MMCLK" Internal fmax is restricted to 275.03 MHz between source register "DREG[0]" and destination register "DREG[15]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.536 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y15_N2; Fanout = 4; REG Node = 'DREG[0]'
            Info: 2: + IC(0.533 ns) + CELL(0.564 ns) = 1.097 ns; Loc. = LC_X2_Y15_N2; Fanout = 2; COMB Node = 'DREG[0]~129'
            Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.175 ns; Loc. = LC_X2_Y15_N3; Fanout = 2; COMB Node = 'DREG[1]~133'
            Info: 4: + IC(0.000 ns) + CELL(0.178 ns) = 1.353 ns; Loc. = LC_X2_Y15_N4; Fanout = 6; COMB Node = 'DREG[2]~137'
            Info: 5: + IC(0.000 ns) + CELL(0.208 ns) = 1.561 ns; Loc. = LC_X2_Y15_N9; Fanout = 6; COMB Node = 'DREG[7]~157'
            Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.697 ns; Loc. = LC_X2_Y14_N4; Fanout = 3; COMB Node = 'DREG[12]~177'
            Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 2.536 ns; Loc. = LC_X2_Y14_N7; Fanout = 2; REG Node = 'DREG[15]'
            Info: Total cell delay = 2.003 ns ( 78.98 % )
            Info: Total interconnect delay = 0.533 ns ( 21.02 % )
        Info: - Smallest clock skew is -0.509 ns
            Info: + Shortest clock path from clock "MMCLK" to destination register is 7.249 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 2; CLK Node = 'MMCLK'
                Info: 2: + IC(3.358 ns) + CELL(0.935 ns) = 5.762 ns; Loc. = LC_X3_Y14_N4; Fanout = 20; REG Node = 'CLK_2'
                Info: 3: + IC(0.776 ns) + CELL(0.711 ns) = 7.249 ns; Loc. = LC_X2_Y14_N7; Fanout = 2; REG Node = 'DREG[15]'
                Info: Total cell delay = 3.115 ns ( 42.97 % )
                Info: Total interconnect delay = 4.134 ns ( 57.03 % )
            Info: - Longest clock path from clock "MMCLK" to source register is 7.758 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 2; CLK Node = 'MMCLK'
                Info: 2: + IC(3.358 ns) + CELL(0.935 ns) = 5.762 ns; Loc. = LC_X3_Y14_N4; Fanout = 20; REG Node = 'CLK_2'
                Info: 3: + IC(1.285 ns) + CELL(0.711 ns) = 7.758 ns; Loc. = LC_X2_Y15_N2; Fanout = 4; REG Node = 'DREG[0]'
                Info: Total cell delay = 3.115 ns ( 40.15 % )
                Info: Total interconnect delay = 4.643 ns ( 59.85 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "MMCLK" to destination pin "GPD[4]" through register "DREG[4]" is 13.214 ns
    Info: + Longest clock path from clock "MMCLK" to source register is 7.758 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 2; CLK Node = 'MMCLK'
        Info: 2: + IC(3.358 ns) + CELL(0.935 ns) = 5.762 ns; Loc. = LC_X3_Y14_N4; Fanout = 20; REG Node = 'CLK_2'
        Info: 3: + IC(1.285 ns) + CELL(0.711 ns) = 7.758 ns; Loc. = LC_X2_Y15_N6; Fanout = 4; REG Node = 'DREG[4]'
        Info: Total cell delay = 3.115 ns ( 40.15 % )
        Info: Total interconnect delay = 4.643 ns ( 59.85 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.232 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y15_N6; Fanout = 4; REG Node = 'DREG[4]'
        Info: 2: + IC(3.124 ns) + CELL(2.108 ns) = 5.232 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'GPD[4]'
        Info: Total cell delay = 2.108 ns ( 40.29 % )
        Info: Total interconnect delay = 3.124 ns ( 59.71 % )
Info: Longest tpd from source pin "MMCLK" to destination pin "USBCLK" is 5.957 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 2; CLK Node = 'MMCLK'
    Info: 2: + IC(2.364 ns) + CELL(2.124 ns) = 5.957 ns; Loc. = PIN_124; Fanout = 0; PIN Node = 'USBCLK'
    Info: Total cell delay = 3.593 ns ( 60.32 % )
    Info: Total interconnect delay = 2.364 ns ( 39.68 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Nov 02 19:50:37 2006
    Info: Elapsed time: 00:00:01