myfx2.v

FPGA与USB通信的测试代码

module MYFX2 (
              nRESET,	PA, GPD,GPA , CTL,RDY,USER, // Inputs from FX2
              IFCLK,CLKOUT, nINT5,// Inputs from FX2

			   USBCLK,		// Output to FX2		  
		       MMCLK,       //from cytal
     		   LED,		    // LED indicator
               KEY,
               RAMAA,RAMAD,RAMAUB,RAMALB,RAMAWE,RAMACE,RAMAOE,
               RAMBA,RAMBD,RAMBUB,RAMBLB,RAMBWE,RAMBCE,RAMBOE
              );
//////////////////////////////////
output [17:0]RAMAA;
output [17:0]RAMBA;
inout  [15:0]RAMAD;
//wire   [15:0]RAMBD;
inout  [15:0]RAMBD;
output RAMAUB,RAMALB,RAMAWE,RAMACE,RAMAOE;
output RAMBUB,RAMBLB,RAMBWE,RAMBCE,RAMBOE;
////////////////////////////////////////////
input nRESET;
///////////////////////////////////
output [7:0]PA;

inout [15:0]GPD;
//wire  [15:0]GPD;
input [8:0]GPA;
input [5:0]CTL;
output [5:0]RDY;
reg  [5:0]RDY;
input [5:0]USER;
input IFCLK,CLKOUT, nINT5;
//////////////////////////////////

input MMCLK;
input [2:0]KEY;

output  [3:0]LED;
reg  [3:0]LED;

reg [15:0]DREG;
reg BLable;


output  USBCLK;
reg  [1:0]      STATE,NEXT;

reg             CLK_2,CLK_4,CLK_8;
wire            HCLK;

parameter     IDLE     = 2'D0,
               WRITE_1  = 2'D1,
               WRITE_2  = 2'D2;

assign USBCLK=MMCLK;
assign PA[4]=0;
assign PA[5]=1;
assign  GPD[15:0]=RDY[1]? 'hz :DREG[15:0];

always @(posedge MMCLK)
 begin
   CLK_2 <= ~CLK_2; 
 end 

always @(posedge CLK_2)
 begin
   CLK_4 <= ~CLK_4; 
 end 


always @(posedge CLK_4)
 begin
   CLK_8 <= ~CLK_8; 
 end 

assign HCLK = CLK_2;



 
//state machine              
 always @ (STATE or LED[0])
 begin
     case(STATE)
     IDLE    : if(LED[0])
                   NEXT = WRITE_1;
               else
                   NEXT = IDLE   ;
     WRITE_1 : NEXT = WRITE_2;
     WRITE_2 : 
               NEXT = WRITE_1;
     default : NEXT = IDLE ;
     endcase
 end
 
 //registe the state
always @(posedge HCLK or negedge KEY[0])
if(!KEY[0])
begin
    STATE <= IDLE;
 
end
 else
    STATE <= NEXT;
 
 
always @(posedge HCLK or negedge KEY[0])
if(!KEY[0])
    begin
        DREG  <=16'hffff;
        RDY[1]      <=1'b1;
        RDY[0]      <=1'b1;
        LED[0]     <= 1'b1;
      //  BLable=1;  
    end
 else
    case(STATE)
    IDLE    : begin
                  RDY[0]     <= 1;
                  RDY[1]     <= 1;
                  

              end
    WRITE_1 : begin
                //  if (BLable==1)
                //  begin
                  DREG <= DREG+1;
                //  if (DREG==255) BLable=0;
				//  end
				//  if (BLable==0)
                //  begin
                //  DREG <= DREG-1;
                //  if (DREG==0) BLable=1;
				//  end
                  RDY[1]     <= 1'b0;
                  RDY[0]     <= 1'b1; 
                     
              end
    WRITE_2 : begin
                  RDY[1]  <= 1'b1;
                  RDY[0]  <= 1'b1;

              end
    endcase


endmodule