mypcio.c

FPGA与USB通信的测试代码

      break;
    }
  
    
	case VX_BE:
    { // turn OFF debug LEDs...
    
        OEA=0xff;
        IOA=0xFE;
      
        *EP0BUF = VX_BE;

  		EP0BCH = 0;
 		EP0BCL = 1;               // Arm endpoint with # bytes to transfer
  		EP0CS |= bmHSNAK;         // Acknowledge handshake phase of device request
  
      break;
    }

   case VX_BF:
    { // turn OFF debug LEDs...
    
        OEA=0xff;
        IOA=0xF7;
      
      *EP0BUF = VX_BF;
       EP0BCH = 0;
       EP0BCL = 1;               // Arm endpoint with # bytes to transfer
       EP0CS |= bmHSNAK;         // Acknowledge handshake phase of device request
  

      break;
    }
   case VX_C3:
    { // turn OFF debug LEDs...
      
       display = TRUE;   

						
     	num=SETUPDAT[2]-0x30; 
		if(display)
		{
			EZUSB_WriteI2C(LED_ADDR, 0x01, &(Digit[num]));
			EZUSB_WaitForEEPROMWrite(LED_ADDR);
			display = FALSE;
		}
                 // Arm endpoint with # bytes to transfer
 *EP0BUF = VX_C3;
  EP0BCH = 0;
  EP0BCL = 1;               // Arm endpoint with # bytes to transfer
  EP0CS |= bmHSNAK;         // Acknowledge handshake phase of device request
  
  
    //  *EP0BUF = VX_C0;
      break;
    }


    case VX_B7:
    { 
      TD_Init( );
      *EP0BUF = VX_B7;
       EP0BCH = 0;
	   EP0BCL = 1;               // Arm endpoint with # bytes to transfer
 	   EP0CS |= bmHSNAK;         // Acknowledge handshake phase of device request
  

      break;
    }
    case VX_B8:
    { 
      EP0BCH = 0;
      EP0BCL = 1;                   // Arm endpoint with # bytes to transfer
      EP0CS |= bmHSNAK;             // Acknowledge handshake phase of device request
      SYNCDELAY;                    // used here as "delay"
      SYNCDELAY;                    // used here as "delay"
      
      EA = 0;             
                      
      // ...do a "soft" code only RESET... vector to ORG 0x0000
      ( ( void ( code * ) ( void ) ) 0x0000 ) ( );
      
      *EP0BUF = VX_B8;
  EP0BCH = 0;
  EP0BCL = 1;               // Arm endpoint with # bytes to transfer
  EP0CS |= bmHSNAK;         // Acknowledge handshake phase of device request
  

      break;
    }
    case VX_BA:
    {                           
      REVCTL = 0x01;            // REVCTL.0=1 (enable enhanced packet handling)
      SYNCDELAY;                // 
      OUTPKTEND = 0x02;         // commit out pkt, w/skip=0
      SYNCDELAY;                // 
      *EP0BUF = VX_BA;
  EP0BCH = 0;
  EP0BCL = 1;               // Arm endpoint with # bytes to transfer
  EP0CS |= bmHSNAK;         // Acknowledge handshake phase of device request
  

      break;
    }
    case VX_BB:
    {                           
      REVCTL = 0x01;            // REVCTL.0=1
      SYNCDELAY;                // 
      INPKTEND = 0x06;          // commit in pkt,  w/skip=0
      SYNCDELAY;                // 
      *EP0BUF = VX_BB;
  EP0BCH = 0;
  EP0BCL = 1;               // Arm endpoint with # bytes to transfer
  EP0CS |= bmHSNAK;         // Acknowledge handshake phase of device request
  

      break;
    }
    case VX_C2:
    { // cpu source out data
      if( EP24FIFOFLGS & 0x02 )
      {
        REVCTL = 0x01;            // ENH_PKT=1 (use enhanced packet handling)
        SYNCDELAY;                // 
        FIFORESET = 0x80;         // nak all OUT pkts. from host
        SYNCDELAY;                // 
        FIFORESET = 0x02;         // advance all EP2 buffers to cpu domain
        SYNCDELAY;                // 
        EP2FIFOBUF[0] = 0xAA;     // create newly sourced pkt. data
        SYNCDELAY;                // 
        EP2BCH = 0x00;
        SYNCDELAY;                // 
        EP2BCL = 0x01;            // commit newly sourced pkt. to interface fifo
      
        // beware of "left over" uncommitted buffers
                                
        SYNCDELAY;                // 
        OUTPKTEND = 0x82;         // skip uncommitted pkt. (second pkt.)
        SYNCDELAY;                // 
        OUTPKTEND = 0x82;         // skip uncommitted pkt. (third pkt.)
        SYNCDELAY;                // 
        OUTPKTEND = 0x82;         // skip uncommitted pkt. (fourth pkt.)
        // note: core will not allow pkts. to get out of sequence
        SYNCDELAY;                // 
        FIFORESET = 0x00;         // release "nak all"
        SYNCDELAY;                // 
      
        *EP0BUF = VX_C2;
  EP0BCH = 0;
  EP0BCL = 1;               // Arm endpoint with # bytes to transfer
  EP0CS |= bmHSNAK;         // Acknowledge handshake phase of device request
  

      }
      else
      {
        *EP0BUF = 0xFF;
  EP0BCH = 0;
  EP0BCL = 1;               // Arm endpoint with # bytes to transfer
  EP0CS |= bmHSNAK;         // Acknowledge handshake phase of device request
  
      }
    
      break;
    }
    default:
    {
      ledX_rdvar = LED3_ON;     // debug visual, stuck "ON" to warn developer...
	    return( FALSE );          // no error; command handled OK
    }
	}
  

	return( FALSE );              // no error; command handled OK
}

//-----------------------------------------------------------------------------
// USB Interrupt Handlers
//   The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------

// Setup Data Available Interrupt Handler
void ISR_Sudav( void ) interrupt 0
{
   GotSUD = TRUE;         // Set flag
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSUDAV;      // Clear SUDAV IRQ
}

// Setup Token Interrupt Handler
void ISR_Sutok( void ) interrupt 0
{
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSUTOK;      // Clear SUTOK IRQ
}

void ISR_Sof( void ) interrupt 0
{
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSOF;        // Clear SOF IRQ
}

void ISR_Ures( void ) interrupt 0
{
   if ( EZUSB_HIGHSPEED( ) )
   {
      pConfigDscr = pHighSpeedConfigDscr;
      pOtherConfigDscr = pFullSpeedConfigDscr;
   }
   else
   {
      pConfigDscr = pFullSpeedConfigDscr;
      pOtherConfigDscr = pHighSpeedConfigDscr;
   }
   
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmURES;       // Clear URES IRQ
}

void ISR_Susp( void ) interrupt 0
{
   Sleep = TRUE;
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSUSP;
}

void ISR_Highspeed( void ) interrupt 0
{
   if ( EZUSB_HIGHSPEED( ) )
   {
      pConfigDscr = pHighSpeedConfigDscr;
      pOtherConfigDscr = pFullSpeedConfigDscr;
   }
   else
   {
      pConfigDscr = pFullSpeedConfigDscr;
      pOtherConfigDscr = pHighSpeedConfigDscr;
   }

   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack( void ) interrupt 0
{
}
void ISR_Stub( void ) interrupt 0
{
}
void ISR_Ep0in( void ) interrupt 0
{
}
void ISR_Ep0out( void ) interrupt 0
{
}
void ISR_Ep1in( void ) interrupt 0
{
}
void ISR_Ep1out( void ) interrupt 0
{
}
void ISR_Ep2inout( void ) interrupt 0
{
}
void ISR_Ep4inout( void ) interrupt 0
{
}
void ISR_Ep6inout( void ) interrupt 0
{
}
void ISR_Ep8inout( void ) interrupt 0
{
}
void ISR_Ibn( void ) interrupt 0
{
}
void ISR_Ep0pingnak( void ) interrupt 0
{
}
void ISR_Ep1pingnak( void ) interrupt 0
{
}
void ISR_Ep2pingnak( void ) interrupt 0
{
}
void ISR_Ep4pingnak( void ) interrupt 0
{
}
void ISR_Ep6pingnak( void ) interrupt 0
{
}
void ISR_Ep8pingnak( void ) interrupt 0
{
}
void ISR_Errorlimit( void ) interrupt 0
{
}
void ISR_Ep2piderror( void ) interrupt 0
{
}
void ISR_Ep4piderror( void ) interrupt 0
{
}
void ISR_Ep6piderror( void ) interrupt 0
{
}
void ISR_Ep8piderror( void ) interrupt 0
{
}
void ISR_Ep2pflag( void ) interrupt 0
{
}
void ISR_Ep4pflag( void ) interrupt 0
{
}
void ISR_Ep6pflag( void ) interrupt 0
{
}
void ISR_Ep8pflag( void ) interrupt 0
{
}
void ISR_Ep2eflag( void ) interrupt 0
{
}
void ISR_Ep4eflag( void ) interrupt 0
{
}
void ISR_Ep6eflag( void ) interrupt 0
{
}
void ISR_Ep8eflag( void ) interrupt 0
{
}
void ISR_Ep2fflag( void ) interrupt 0
{
}
void ISR_Ep4fflag( void ) interrupt 0
{
}
void ISR_Ep6fflag( void ) interrupt 0
{
}
void ISR_Ep8fflag( void ) interrupt 0
{
}
void ISR_GpifComplete( void ) interrupt 0
{
}
void ISR_GpifWaveform( void ) interrupt 0
{
}