📄 mypcio.lst
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235 #define VX_C2 0xC2 // source out pkt.
236
237
238 #define VX_BC 0xBC // turn OFF debug LEDs...
239 #define VX_BD 0xBD // turn OFF debug LEDs...
C51 COMPILER V7.50 MYPCIO 09/18/2006 19:53:27 PAGE 5
240 #define VX_BE 0xBE // turn OFF debug LEDs...
241 #define VX_BF 0xBF // turn OFF debug LEDs...
242
243 #define VX_C3 0xC3 // turn OFF debug LEDs...
244
245
246 // Core uses bRequest value 0xA0 for Anchor downloads/uploads...
247 // Cypress Semiconductor reserves bRequest values 0xA1 through 0xAF...
248 // Your implementation should not use the above bRequest values...
249 // Also, previous fw.c versions trap all bRequest values 0x00 through 0x0F...
250 //
251 // bRequest value: SETUPDAT[1]
252 // standard, 0x00 through 0x0F
253 //
254 // bmRequest value: SETUPDAT[0]
255 // standard, 0x80 IN Token
256 // vendor, 0xC0 IN Token
257 // class, 0xA0 IN Token
258 // standard, 0x00 OUT Token
259 // vendor, 0x40 OUT Token
260 // class, 0x60 OUT Token
261
262 BOOL DR_VendorCmnd( void )
263 {
264 1
265 1 // Registers which require a synchronization delay, see section 15.14
266 1 // FIFORESET FIFOPINPOLAR
267 1 // INPKTEND OUTPKTEND
268 1 // EPxBCH:L REVCTL
269 1 // GPIFTCB3 GPIFTCB2
270 1 // GPIFTCB1 GPIFTCB0
271 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
272 1 // EPxFIFOCFG EPxGPIFFLGSEL
273 1 // PINFLAGSxx EPxFIFOIRQ
274 1 // EPxFIFOIE GPIFIRQ
275 1 // GPIFIE GPIFADRH:L
276 1 // UDMACRCH:L EPxGPIFTRIG
277 1 // GPIFTRIG
278 1
279 1 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
280 1 // ...these have been replaced by GPIFTC[B3:B0] registers
281 1
282 1
283 1
284 1
285 1 switch( SETUPDAT[ 1 ] )
286 1 {
287 2 case VX_B2:
288 2 { // turn OFF debug LEDs...
289 3
290 3 ledX_rdvar = LED0_ON; // visual
291 3 ledX_rdvar = LED1_ON; // visual
292 3 ledX_rdvar = LED2_ON; // visual
293 3 ledX_rdvar = LED3_ON; // visual
294 3
295 3 *EP0BUF = VX_B2;
296 3
297 3 EP0BCH = 0;
298 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
299 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
300 3
301 3
C51 COMPILER V7.50 MYPCIO 09/18/2006 19:53:27 PAGE 6
302 3 break;
303 3 }
304 2 case VX_B3:
305 2 { // turn OFF debug LEDs...
306 3
307 3 ledX_rdvar = LED0_OFF; // visual
308 3 ledX_rdvar = LED1_OFF; // visual
309 3 ledX_rdvar = LED2_OFF; // visual
310 3 ledX_rdvar = LED3_OFF; // visual
311 3
312 3 *EP0BUF = VX_B3;
313 3 EP0BCH = 0;
314 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
315 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
316 3
317 3
318 3
319 3
320 3 break;
321 3 }
322 2
323 2 case VX_BC:
324 2 { // turn OFF debug LEDs...
325 3
326 3 OEA=0xff;
327 3 IOA=0xFD;
328 3
329 3 *EP0BUF = VX_BC;
330 3 EP0BCH = 0;
331 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
332 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
333 3
334 3
335 3
336 3
337 3
338 3
339 3
340 3
341 3 break;
342 3 }
343 2
344 2 case VX_BD:
345 2 { // turn OFF debug LEDs...
346 3 OEA=0xff;
347 3 IOA=0xFB;
348 3
349 3 *EP0BUF = VX_BD;
350 3 EP0BCH = 0;
351 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
352 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
353 3
354 3
355 3
356 3 break;
357 3 }
358 2
359 2
360 2 case VX_BE:
361 2 { // turn OFF debug LEDs...
362 3
363 3 OEA=0xff;
C51 COMPILER V7.50 MYPCIO 09/18/2006 19:53:27 PAGE 7
364 3 IOA=0xFE;
365 3
366 3 *EP0BUF = VX_BE;
367 3
368 3 EP0BCH = 0;
369 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
370 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
371 3
372 3 break;
373 3 }
374 2
375 2 case VX_BF:
376 2 { // turn OFF debug LEDs...
377 3
378 3 OEA=0xff;
379 3 IOA=0xF7;
380 3
381 3 *EP0BUF = VX_BF;
382 3 EP0BCH = 0;
383 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
384 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
385 3
386 3
387 3 break;
388 3 }
389 2 case VX_C3:
390 2 { // turn OFF debug LEDs...
391 3
392 3 display = TRUE;
393 3
394 3
395 3 num=SETUPDAT[2]-0x30;
396 3 if(display)
397 3 {
398 4 EZUSB_WriteI2C(LED_ADDR, 0x01, &(Digit[num]));
399 4 EZUSB_WaitForEEPROMWrite(LED_ADDR);
400 4 display = FALSE;
401 4 }
402 3 // Arm endpoint with # bytes to transfer
403 3 *EP0BUF = VX_C3;
404 3 EP0BCH = 0;
405 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
406 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
407 3
408 3
409 3 // *EP0BUF = VX_C0;
410 3 break;
411 3 }
412 2
413 2
414 2 case VX_B7:
415 2 {
416 3 TD_Init( );
417 3 *EP0BUF = VX_B7;
418 3 EP0BCH = 0;
419 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
420 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
421 3
422 3
423 3 break;
424 3 }
425 2 case VX_B8:
C51 COMPILER V7.50 MYPCIO 09/18/2006 19:53:27 PAGE 8
426 2 {
427 3 EP0BCH = 0;
428 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
429 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
430 3 SYNCDELAY; // used here as "delay"
431 3 SYNCDELAY; // used here as "delay"
432 3
433 3 EA = 0;
434 3
435 3 // ...do a "soft" code only RESET... vector to ORG 0x0000
436 3 ( ( void ( code * ) ( void ) ) 0x0000 ) ( );
437 3
438 3 *EP0BUF = VX_B8;
439 3 EP0BCH = 0;
440 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
441 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
442 3
443 3
444 3 break;
445 3 }
446 2 case VX_BA:
447 2 {
448 3 REVCTL = 0x01; // REVCTL.0=1 (enable enhanced packet handling)
449 3 SYNCDELAY; //
450 3 OUTPKTEND = 0x02; // commit out pkt, w/skip=0
451 3 SYNCDELAY; //
452 3 *EP0BUF = VX_BA;
453 3 EP0BCH = 0;
454 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
455 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
456 3
457 3
458 3 break;
459 3 }
460 2 case VX_BB:
461 2 {
462 3 REVCTL = 0x01; // REVCTL.0=1
463 3 SYNCDELAY; //
464 3 INPKTEND = 0x06; // commit in pkt, w/skip=0
465 3 SYNCDELAY; //
466 3 *EP0BUF = VX_BB;
467 3 EP0BCH = 0;
468 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
469 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
470 3
471 3
472 3 break;
473 3 }
474 2 case VX_C2:
475 2 { // cpu source out data
476 3 if( EP24FIFOFLGS & 0x02 )
477 3 {
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