📄 mypcio.lst
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C51 COMPILER V7.50 MYPCIO 09/18/2006 19:53:27 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE MYPCIO
OBJECT MODULE PLACED IN MYPCIO.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE MYPCIO.c BROWSE DEBUG OBJECTEXTEND
line level source
1 #pragma NOIV // Do not generate interrupt vectors
2 //-----------------------------------------------------------------------------
3 // File: srcout_s.c
4 // Contents: Hooks required to implement USB peripheral function.
5 // Code written for EZUSB FX2 128-pin REVE...
6 // Firmware tested on EZUSB FX2 128-pin (CY3681 DK)
7 // Copyright (c) 2001 Cypress Semiconductor All rights reserved
8 //-----------------------------------------------------------------------------
9 #include "fx2.h"
10 #include "fx2regs.h"
11 #include "fx2sdly.h" // SYNCDELAY macro
12
13 extern BOOL GotSUD; // Received setup data flag
14 extern BOOL Sleep;
15 extern BOOL Rwuen;
16 extern BOOL Selfpwr;
17
18 BYTE Configuration; // Current configuration
19 BYTE AlternateSetting; // Alternate settings
20
21 // ...debug LEDs: accessed via movx reads only ( through CPLD )
22 xdata volatile const BYTE LED0_ON _at_ 0x8000;
23 xdata volatile const BYTE LED0_OFF _at_ 0x8100;
24 xdata volatile const BYTE LED1_ON _at_ 0x9000;
25 xdata volatile const BYTE LED1_OFF _at_ 0x9100;
26 xdata volatile const BYTE LED2_ON _at_ 0xA000;
27 xdata volatile const BYTE LED2_OFF _at_ 0xA100;
28 xdata volatile const BYTE LED3_ON _at_ 0xB000;
29 xdata volatile const BYTE LED3_OFF _at_ 0xB100;
30 // it may be worth noting here that the default monitor loads at 0xC000
31
32 // use this global variable when (de)asserting debug LEDs...
33 BYTE ledX_rdvar = 0x00;
34
35 //BYTE xdata Digit[] = { 0xc0, 0xf9, 0xa4, 0xb0, 0x99, 0x92, 0x82, 0xf8, 0x80, 0x98, 0x88, 0x83, 0xc6, 0xa
-1, 0x86, 0x8e };
36 BYTE xdata Digit[] = { 0xC0, 0xf9, 0x64, 0x46, 0x4b, 0x52, 0x50, 0xc7, 0x40, 0x43, 0x41, 0x58, 0xf0, 0x4c,
- 0x70, 0x71 };
37
38 #define BTN_ADDR 0x38
39 #define LED_ADDR 0x39
40
41 BYTE num = 0;
42 BYTE display = TRUE;
43 //-----------------------------------------------------------------------------
44 // Task Dispatcher hooks
45 // The following hooks are called by the task dispatcher.
46 //-----------------------------------------------------------------------------
47 void TD_Init( void )
48 { // Called once at startup
49 1
50 1 CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation
51 1 // CLKOE=0, don't drive CLKOUT
52 1
53 1 IFCONFIG = 0xCB;
C51 COMPILER V7.50 MYPCIO 09/18/2006 19:53:27 PAGE 2
54 1 // IFCLKSRC=1 , FIFOs executes on internal clk source
55 1 // xMHz=1 , 48MHz internal clk rate
56 1 // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
57 1 // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
58 1 // ASYNC=1 , master samples asynchronous
59 1 // GSTATE=0 , Don't drive GPIF states out on PORTE[2:0], debug WF
60 1 // IFCFG[1:0]=11, FX2 in slave FIFO mode
61 1
62 1
63 1 // Registers which require a synchronization delay, see section 15.14
64 1 // FIFORESET FIFOPINPOLAR
65 1 // INPKTEND OUTPKTEND
66 1 // EPxBCH:L REVCTL
67 1 // GPIFTCB3 GPIFTCB2
68 1 // GPIFTCB1 GPIFTCB0
69 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
70 1 // EPxFIFOCFG EPxGPIFFLGSEL
71 1 // PINFLAGSxx EPxFIFOIRQ
72 1 // EPxFIFOIE GPIFIRQ
73 1 // GPIFIE GPIFADRH:L
74 1 // UDMACRCH:L EPxGPIFTRIG
75 1 // GPIFTRIG
76 1
77 1 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
78 1 // ...these have been replaced by GPIFTC[B3:B0] registers
79 1
80 1 SYNCDELAY; // see TRM section 15.14
81 1 REVCTL = 0x01; // use enhanced packet handling
82 1
83 1 // NOTE: when using "enhanced packet handling" feature (REVCTL.0=1)
84 1 // ...the core functions as follows:
85 1 // - OUTPKTEND is used to skip/commit OUT pkt.
86 1 // - INPKTEND is used to skip/commit IN pkt.
87 1 // - EPxBCH/L is used to
88 1 // - commit cpu sourced pkt.
89 1 // - modify length of an OUT pkt.
90 1 // - cpu can not source an OUT pkt in "AUTOOUT" mode
91 1 // - see cpu source out pkt method in BOOL DR_VendorCmnd(); ...
92 1
93 1 // EP2 512 BULK OUT 4x
94 1 SYNCDELAY; //
95 1 EP2CFG = 0xA0; // BUF[1:0]=00 for 4x buffering
96 1
97 1 // EP6 512 BULK IN 4x
98 1 SYNCDELAY; //
99 1 EP6CFG = 0xE0; // BUF[1:0]=00 for 4x buffering
100 1
101 1 // EP4 and EP8 are not used in this implementation...
102 1 SYNCDELAY; //
103 1 EP4CFG = 0x20; // clear valid bit
104 1 SYNCDELAY; //
105 1 EP8CFG = 0x60; // clear valid bit
106 1
107 1 SYNCDELAY; //
108 1 FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
109 1 SYNCDELAY; //
110 1 FIFORESET = 0x02; // reset, FIFO 2
111 1 SYNCDELAY; //
112 1 FIFORESET = 0x04; // reset, FIFO 4
113 1 SYNCDELAY; //
114 1 FIFORESET = 0x06; // reset, FIFO 6
115 1 SYNCDELAY; //
C51 COMPILER V7.50 MYPCIO 09/18/2006 19:53:27 PAGE 3
116 1 FIFORESET = 0x08; // reset, FIFO 8
117 1 SYNCDELAY; //
118 1 FIFORESET = 0x00; // deactivate NAK-ALL
119 1
120 1 // 8-bit bus (WORDWIDE=0)...
121 1
122 1 // use manual out mode...
123 1 SYNCDELAY; //
124 1 EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=0
125 1
126 1 SYNCDELAY; //
127 1 OUTPKTEND = 0x82; // arm first buffer
128 1 SYNCDELAY; //
129 1 OUTPKTEND = 0x82; // arm second buffer
130 1 SYNCDELAY; //
131 1 OUTPKTEND = 0x82; // arm third buffer
132 1 SYNCDELAY; //
133 1 OUTPKTEND = 0x82; // arm fourth buffer
134 1
135 1 // use auto in mode
136 1 SYNCDELAY; //
137 1 EP6FIFOCFG = 0x0C; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0
138 1 }
139
140 void TD_Poll( void )
141 { // Called repeatedly while the device is idle
142 1
143 1 // see BOOL DR_VendorCmnd( void );
144 1 // ...core "auto" commits pkts using EP6AUTOINLENH/L value
145 1
146 1 }
147
148 BOOL TD_Suspend( void )
149 { // Called before the device goes into suspend mode
150 1 return( TRUE );
151 1 }
152
153 BOOL TD_Resume( void )
154 { // Called after the device resumes
155 1 return( TRUE );
156 1 }
157
158 //-----------------------------------------------------------------------------
159 // Device Request hooks
160 // The following hooks are called by the end point 0 device request parser.
161 //-----------------------------------------------------------------------------
162 BOOL DR_GetDescriptor( void )
163 {
164 1 return( TRUE );
165 1 }
166
167 BOOL DR_SetConfiguration( void )
168 { // Called when a Set Configuration command is received
169 1
170 1 if( EZUSB_HIGHSPEED( ) )
171 1 { // ...FX2 in high speed mode
172 2 SYNCDELAY; //
173 2 EP6AUTOINLENH = 0x02; // set core AUTO commit len = 512 bytes
174 2 SYNCDELAY; //
175 2 EP6AUTOINLENL = 0x00;
176 2 SYNCDELAY; //
177 2 }
C51 COMPILER V7.50 MYPCIO 09/18/2006 19:53:27 PAGE 4
178 1 else
179 1 { // ...FX2 in full speed mode
180 2 SYNCDELAY; //
181 2 EP6AUTOINLENH = 0x00; // set core AUTO commit len = 64 bytes
182 2 SYNCDELAY; //
183 2 EP6AUTOINLENL = 0x40;
184 2 SYNCDELAY; //
185 2 }
186 1
187 1 Configuration = SETUPDAT[ 2 ];
188 1 return( TRUE ); // Handled by user code
189 1 }
190
191 BOOL DR_GetConfiguration( void )
192 { // Called when a Get Configuration command is received
193 1 EP0BUF[ 0 ] = Configuration;
194 1 EP0BCH = 0;
195 1 EP0BCL = 1;
196 1 return(TRUE); // Handled by user code
197 1 }
198
199 BOOL DR_SetInterface( void )
200 { // Called when a Set Interface command is received
201 1 AlternateSetting = SETUPDAT[ 2 ];
202 1 return( TRUE ); // Handled by user code
203 1 }
204
205 BOOL DR_GetInterface( void )
206 { // Called when a Set Interface command is received
207 1 EP0BUF[ 0 ] = AlternateSetting;
208 1 EP0BCH = 0;
209 1 EP0BCL = 1;
210 1 return( TRUE ); // Handled by user code
211 1 }
212
213 BOOL DR_GetStatus( void )
214 {
215 1 return( TRUE );
216 1 }
217
218 BOOL DR_ClearFeature( void )
219 {
220 1 return( TRUE );
221 1 }
222
223 BOOL DR_SetFeature( void )
224 {
225 1 return( TRUE );
226 1 }
227
228 #define VX_B2 0xB2 // turn ON debug LEDs...
229 #define VX_B3 0xB3 // turn OFF debug LEDs...
230
231 #define VX_B7 0xB7 // re-initialize, call TD_Init( );
232 #define VX_B8 0xB8 // do a "soft reset", vector to org 00h
233 #define VX_BA 0xBA // commit out pkt. new way
234 #define VX_BB 0xBB // commit in pkt. new way
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