myfx2.v

来自「FPGA与USB通信的测试代码」· Verilog 代码 · 共 53 行

module MYFX2 (
              nRESET,	PA, GPD,GPA , CTL,RDY,USER, // Inputs from FX2
              IFCLK,CLKOUT, nINT5,// Inputs from FX2

			   USBCLK,		// Output to FX2		  
		       MMCLK,       //from cytal
     		   LED,		    // LED indicator
               KEY,
               RAMAA,RAMAD,RAMAUB,RAMALB,RAMAWE,RAMACE,RAMAOE,
               RAMBA,RAMBD,RAMBUB,RAMBLB,RAMBWE,RAMBCE,RAMBOE,
              );
//////////////////////////////////
output [17:0]RAMAA;
output [17:0]RAMBA;
inout  [15:0]RAMAD;
inout  [15:0]RAMBD;
output RAMAUB,RAMALB,RAMAWE,RAMACE,RAMAOE;
output RAMBUB,RAMBLB,RAMBWE,RAMBCE,RAMBOE;
////////////////////////////////////////////
input nRESET;
///////////////////////////////////
input [7:0]PA;
input [15:0]GPD;
input [8:0]GPA;
input [5:0]CTL;
input [5:0]RDY;
input [5:0]USER;
input IFCLK,CLKOUT, nINT5;
//////////////////////////////////

input MMCLK;
input [2:0]KEY;

output  [3:0]LED;
//reg [3:0]LED;


output  USBCLK;


assign USBCLK=MMCLK;



assign LED[3:0]=PA[3:0];




												
endmodule