kkd.tan.rpt

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源码 开发软件 Quartus II

; Clock Setup: 'dsp_clk'       ; 1.379 ns  ; 100.00 MHz ( period = 10.000 ns ) ; 116.00 MHz ( period = 8.621 ns ) ; test_cpld_to_dsp:inst66|now_st.D4     ; test_cpld_to_dsp:inst66|data_out[1]         ; dsp_clk      ; dsp_clk      ; 0            ;
; Clock Setup: 'pwm_from_dsc'  ; 3.605 ns  ; 100.00 MHz ( period = 10.000 ns ) ; 156.37 MHz ( period = 6.395 ns ) ; fenpin200:inst21|cnt[0]               ; fenpin200:inst21|cnt[6]                     ; pwm_from_dsc ; pwm_from_dsc ; 0            ;
; Clock Setup: 'pwm_fp_cs'     ; 3.605 ns  ; 100.00 MHz ( period = 10.000 ns ) ; 156.37 MHz ( period = 6.395 ns ) ; fenpin200:inst21|cnt[0]               ; fenpin200:inst21|cnt[6]                     ; pwm_fp_cs    ; pwm_fp_cs    ; 0            ;
; Clock Hold: 'CLK'            ; -4.106 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; dram_tmp:inst46|ad_lz_out[24]         ; trig_two_to_one:inst16|cc1                  ; CLK          ; CLK          ; 1            ;
; Clock Hold: 'dsp_clk'        ; 1.410 ns  ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; test_cpld_to_dsp:inst66|now_st.D20    ; test_cpld_to_dsp:inst66|now_st.D21          ; dsp_clk      ; dsp_clk      ; 0            ;
; Clock Hold: 'pwm_from_dsc'   ; 1.670 ns  ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; fenpin200:inst21|cnt[5]               ; fenpin200:inst21|clk_divi                   ; pwm_from_dsc ; pwm_from_dsc ; 0            ;
; Clock Hold: 'pwm_fp_cs'      ; 1.670 ns  ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; fenpin200:inst21|cnt[5]               ; fenpin200:inst21|clk_divi                   ; pwm_fp_cs    ; pwm_fp_cs    ; 0            ;
; Total number of failed paths ;           ;                                   ;                                  ;                                       ;                                             ;              ;              ; 132          ;
+------------------------------+-----------+-----------------------------------+----------------------------------+---------------------------------------+---------------------------------------------+--------------+--------------+--------------+


+----------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                       ;
+-------------------------------------------------------+--------------------+------+--------------+-------------+
; Option                                                ; Setting            ; From ; To           ; Entity Name ;
+-------------------------------------------------------+--------------------+------+--------------+-------------+
; Device Name                                           ; EPM1270T144C5      ;      ;              ;             ;
; Timing Models                                         ; Final              ;      ;              ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;              ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;              ;             ;
; Cut off read during write signal paths                ; On                 ;      ;              ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;              ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;              ;             ;
; fmax Requirement                                      ; 100 MHz            ;      ;              ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;              ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;              ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;              ;             ;
; Enable Clock Latency                                  ; Off                ;      ;              ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;              ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;              ;             ;
; Number of paths to report                             ; 200                ;      ;              ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;              ;             ;
; Use Fast Timing Models                                ; Off                ;      ;              ;             ;
; Report IO Paths Separately                            ; Off                ;      ;              ;             ;
; Clock Settings                                        ; clk                ;      ; CLK          ;             ;
; Clock Settings                                        ; clk_dsp            ;      ; dsp_clk      ;             ;
; Clock Settings                                        ; cs_clk             ;      ; pwm_fp_cs    ;             ;
; Clock Settings                                        ; pwm_clk            ;      ; pwm_from_dsc ;             ;
+-------------------------------------------------------+--------------------+------+--------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ; clk                ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pwm_from_dsc    ; pwm_clk            ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pwm_fp_cs       ; cs_clk             ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; dsp_clk         ; clk_dsp            ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------+---------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                    ; To                                          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;