mux2.v

来自「基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源」· Verilog 代码 · 共 33 行

module mux2(sect,vovo,clk_con,din1,din2,addr,dout0);
input  din1;
input  din2;
input  addr;
input  vovo;
input  sect;
input  clk_con;
output dout0;
reg    dout0;

always @(sect or addr or din1 or din2 or clk_con or vovo)
begin
if(!vovo)
   begin
     if(sect==1'b1)
     dout0<=din1;
     else
     case(addr)
         1'b0:dout0<=din1;             
         1'b1:dout0<=din2;            
      default:dout0<=1'bx;             
     endcase
   end
else
   begin
   if(!clk_con)
      dout0<=din1;
   else
      dout0<=din2;
   end 
end

endmodule