com_to_lpt.v

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源码 开发软件 Quartus II

module com_to_lpt(clk,clk_n,stopt,rst,data_buf,st,chi,clk_out,voi,sel,data_o);
input       clk,rst;
input       clk_n;
input       stopt;
input[7:0]  data_buf;
output      clk_out;
output      st;
output      chi;
output      sel;
output[7:0] data_o;
output      voi;
reg         clk_out;
reg[7:0]    data_o;
reg         st;
reg         chi;
reg         sell;
reg         sel;
reg         voi;
reg[3:0]    current_state;
reg[3:0]    next_state;
reg         term1;

parameter   S0=4'b0000;     //状态机的13个顺序状态
parameter   S1=4'b0001;
parameter   S2=4'b0010;
parameter   S3=4'b0011;
parameter   S4=4'b0100;
parameter   S5=4'b0101;
parameter   S6=4'b0110;
parameter   S7=4'b0111;
parameter   S8=4'b1000;
parameter   S9=4'b1001;
parameter   S10=4'b1010;
parameter   S11=4'b1011;
parameter   S12=4'b1100;

always @(posedge clk or negedge rst)
begin
   if(!rst)
     current_state<=4'b0;
   else
     current_state<=next_state;
end

always @(term1 or current_state or voi)
begin
   case(current_state)
       S0:if(term1==1'b1)
              begin
                 next_state<=S1;
                 if(voi==1'b0)
                    voi<=1'b0;
                 else
                    voi<=1'b1;
              end 
          else
              begin
                 next_state<=S0;
                 if(voi==1'b0)
                    voi<=1'b0;
                 else
                    voi<=1'b1;
              end  
       S1:begin
          next_state<=S2;
          if(voi==1'b0)
             voi<=1'b0;
          else
             voi<=1'b1;
          end
       S2:if(term1==1'b1)
              begin
              next_state<=S3;
              voi<=1'b0;
              end
          else
              begin
              next_state<=S0;
              voi<=1'b1;
              end
       S3:begin
          next_state<=S4;
          if(voi==1'b0)
             voi<=1'b0;
          else
             voi<=1'b1;
          end
       S4:begin
          next_state<=S5;
          if(voi==1'b0)
             voi<=1'b0;
          else
             voi<=1'b1;
          end
       S5:begin
          next_state<=S6;
          if(voi==1'b0)
             voi<=1'b0;
          else
             voi<=1'b1;
          end
       S6:begin
          next_state<=S7;
          if(voi==1'b0)
             voi<=1'b0;
          else
             voi<=1'b1;
          end
       S7:begin
          next_state<=S8;
          if(voi==1'b0)
             voi<=1'b0;
          else
             voi<=1'b1;
          end
       S8:begin
          next_state<=S9;
          if(voi==1'b0)
             voi<=1'b0;
          else
             voi<=1'b1;
          end
       S9:begin
          next_state<=S10;
          if(voi==1'b0)
             voi<=1'b0;
          else
             voi<=1'b1;
          end
       S10:begin
          next_state<=S11;
          if(voi==1'b0)
             voi<=1'b0;
          else
             voi<=1'b1;
          end
       S11:begin
          next_state<=S12;
          if(voi==1'b0)
             voi<=1'b0;
          else
             voi<=1'b1;
          end
       S12:begin
          next_state<=S0;
          if(voi==1'b0)
             voi<=1'b0;
          else
             voi<=1'b1;
          end
  default:begin
          next_state<=S0;
          voi<=1'b0;
          end
   endcase
end

always @(posedge clk or negedge rst)
begin
   if(!rst)
   term1<=1'b0;
   else if(stopt==1'b1)
   term1<=1'b0;
   else
   term1<=1'b1;
end

always @(posedge clk or negedge rst)
begin
if(!rst)
   data_o<=8'b11111111;
else if(next_state==S1)
   data_o<=data_buf;
else
   data_o<=data_o;
end

always @(posedge clk or negedge rst)
begin
if(!rst)
  st<=1'b1;
else if(next_state==S2)
  st<=1'b0;
else if(next_state==S4)
  st<=1'b1;
else
  st<=st;
end

always @(posedge clk or negedge rst)
begin
if(!rst)
  begin
  chi<=1'b1;
  clk_out<=1'b0;
  sell<=1'b0;
  end
else if(next_state==S5)
  begin
  chi<=1'b0;
  clk_out<=1'b1;
  sell<=1'b0;
  end
else if(next_state==S12)
  begin
  chi<=1'b1;
  sell<=1'b1;
  clk_out<=clk_out;
  end
else if(next_state==S0)
  begin
  chi<=chi;
  sell<=sell;
  clk_out<=1'b0;
  end
else if(next_state==S1)
  begin
  chi<=chi;
  sell<=1'b0;
  clk_out<=clk_out;
  end
else
  begin
  sell<=1'b0;
  chi<=chi;
  clk_out<=clk_out;
  end
end

always @(posedge clk_n or negedge rst)
begin
if(!rst)
sel<=1'b0;
else if(sell==1'b1)
sel<=1'b1;
else
sel<=1'b0;
end

endmodule