prev_cmp_kkd.tan.qmsg

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源码 开发软件 Quartus II

{ "Info" "ITDB_FULL_SLACK_RESULT" "pwm_fp_cs register fenpin200:inst21\|cnt\[0\] register fenpin200:inst21\|cnt\[6\] 3.629 ns " "Info: Slack time is 3.629 ns for clock \"pwm_fp_cs\" between source register \"fenpin200:inst21\|cnt\[0\]\" and destination register \"fenpin200:inst21\|cnt\[6\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "156.96 MHz 6.371 ns " "Info: Fmax is 156.96 MHz (period= 6.371 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.291 ns + Largest register register " "Info: + Largest register to register requirement is 9.291 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pwm_fp_cs 10.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"pwm_fp_cs\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pwm_fp_cs 10.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"pwm_fp_cs\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pwm_fp_cs destination 6.118 ns + Shortest register " "Info: + Shortest clock path from clock \"pwm_fp_cs\" to destination register is 6.118 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns pwm_fp_cs 1 CLK PIN_134 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_134; Fanout = 2; CLK Node = 'pwm_fp_cs'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm_fp_cs } "NODE_NAME" } } { "kkd.bdf" "" { Schematic "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/kkd.bdf" { { 2136 264 432 2152 "pwm_fp_cs" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.869 ns) + CELL(0.511 ns) 4.512 ns two_mux:inst18\|dout0 2 COMB LC_X7_Y4_N9 9 " "Info: 2: + IC(2.869 ns) + CELL(0.511 ns) = 4.512 ns; Loc. = LC_X7_Y4_N9; Fanout = 9; COMB Node = 'two_mux:inst18\|dout0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.380 ns" { pwm_fp_cs two_mux:inst18|dout0 } "NODE_NAME" } } { "two_mux.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/two_mux.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(0.918 ns) 6.118 ns fenpin200:inst21\|cnt\[6\] 3 REG LC_X7_Y4_N2 5 " "Info: 3: + IC(0.688 ns) + CELL(0.918 ns) = 6.118 ns; Loc. = LC_X7_Y4_N2; Fanout = 5; REG Node = 'fenpin200:inst21\|cnt\[6\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.606 ns" { two_mux:inst18|dout0 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.561 ns ( 41.86 % ) " "Info: Total cell delay = 2.561 ns ( 41.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.557 ns ( 58.14 % ) " "Info: Total interconnect delay = 3.557 ns ( 58.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.118 ns" { pwm_fp_cs two_mux:inst18|dout0 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.118 ns" { pwm_fp_cs {} pwm_fp_cs~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[6] {} } { 0.000ns 0.000ns 2.869ns 0.688ns } { 0.000ns 1.132ns 0.511ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pwm_fp_cs source 6.118 ns - Longest register " "Info: - Longest clock path from clock \"pwm_fp_cs\" to source register is 6.118 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns pwm_fp_cs 1 CLK PIN_134 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_134; Fanout = 2; CLK Node = 'pwm_fp_cs'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm_fp_cs } "NODE_NAME" } } { "kkd.bdf" "" { Schematic "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/kkd.bdf" { { 2136 264 432 2152 "pwm_fp_cs" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.869 ns) + CELL(0.511 ns) 4.512 ns two_mux:inst18\|dout0 2 COMB LC_X7_Y4_N9 9 " "Info: 2: + IC(2.869 ns) + CELL(0.511 ns) = 4.512 ns; Loc. = LC_X7_Y4_N9; Fanout = 9; COMB Node = 'two_mux:inst18\|dout0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.380 ns" { pwm_fp_cs two_mux:inst18|dout0 } "NODE_NAME" } } { "two_mux.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/two_mux.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(0.918 ns) 6.118 ns fenpin200:inst21\|cnt\[0\] 3 REG LC_X7_Y4_N8 4 " "Info: 3: + IC(0.688 ns) + CELL(0.918 ns) = 6.118 ns; Loc. = LC_X7_Y4_N8; Fanout = 4; REG Node = 'fenpin200:inst21\|cnt\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.606 ns" { two_mux:inst18|dout0 fenpin200:inst21|cnt[0] } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.561 ns ( 41.86 % ) " "Info: Total cell delay = 2.561 ns ( 41.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.557 ns ( 58.14 % ) " "Info: Total interconnect delay = 3.557 ns ( 58.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.118 ns" { pwm_fp_cs two_mux:inst18|dout0 fenpin200:inst21|cnt[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.118 ns" { pwm_fp_cs {} pwm_fp_cs~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[0] {} } { 0.000ns 0.000ns 2.869ns 0.688ns } { 0.000ns 1.132ns 0.511ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.118 ns" { pwm_fp_cs two_mux:inst18|dout0 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.118 ns" { pwm_fp_cs {} pwm_fp_cs~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[6] {} } { 0.000ns 0.000ns 2.869ns 0.688ns } { 0.000ns 1.132ns 0.511ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.118 ns" { pwm_fp_cs two_mux:inst18|dout0 fenpin200:inst21|cnt[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.118 ns" { pwm_fp_cs {} pwm_fp_cs~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[0] {} } { 0.000ns 0.000ns 2.869ns 0.688ns } { 0.000ns 1.132ns 0.511ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns - " "Info: - Micro setup delay of destination is 0.333 ns" {  } { { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 11 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.118 ns" { pwm_fp_cs two_mux:inst18|dout0 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.118 ns" { pwm_fp_cs {} pwm_fp_cs~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[6] {} } { 0.000ns 0.000ns 2.869ns 0.688ns } { 0.000ns 1.132ns 0.511ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.118 ns" { pwm_fp_cs two_mux:inst18|dout0 fenpin200:inst21|cnt[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.118 ns" { pwm_fp_cs {} pwm_fp_cs~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[0] {} } { 0.000ns 0.000ns 2.869ns 0.688ns } { 0.000ns 1.132ns 0.511ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.662 ns - Longest register register " "Info: - Longest register to register delay is 5.662 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fenpin200:inst21\|cnt\[0\] 1 REG LC_X7_Y4_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y4_N8; Fanout = 4; REG Node = 'fenpin200:inst21\|cnt\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { fenpin200:inst21|cnt[0] } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.319 ns) + CELL(0.747 ns) 2.066 ns fenpin200:inst21\|Add0~132 2 COMB LC_X6_Y4_N0 2 " "Info: 2: + IC(1.319 ns) + CELL(0.747 ns) = 2.066 ns; Loc. = LC_X6_Y4_N0; Fanout = 2; COMB Node = 'fenpin200:inst21\|Add0~132'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.066 ns" { fenpin200:inst21|cnt[0] fenpin200:inst21|Add0~132 } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.189 ns fenpin200:inst21\|Add0~130 3 COMB LC_X6_Y4_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.189 ns; Loc. = LC_X6_Y4_N1; Fanout = 2; COMB Node = 'fenpin200:inst21\|Add0~130'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { fenpin200:inst21|Add0~132 fenpin200:inst21|Add0~130 } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.312 ns fenpin200:inst21\|Add0~124 4 COMB LC_X6_Y4_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.312 ns; Loc. = LC_X6_Y4_N2; Fanout = 2; COMB Node = 'fenpin200:inst21\|Add0~124'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { fenpin200:inst21|Add0~130 fenpin200:inst21|Add0~124 } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.435 ns fenpin200:inst21\|Add0~128 5 COMB LC_X6_Y4_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.435 ns; Loc. = LC_X6_Y4_N3; Fanout = 2; COMB Node = 'fenpin200:inst21\|Add0~128'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { fenpin200:inst21|Add0~124 fenpin200:inst21|Add0~128 } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 2.696 ns fenpin200:inst21\|Add0~126 6 COMB LC_X6_Y4_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.261 ns) = 2.696 ns; Loc. = LC_X6_Y4_N4; Fanout = 3; COMB Node = 'fenpin200:inst21\|Add0~126'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.261 ns" { fenpin200:inst21|Add0~128 fenpin200:inst21|Add0~126 } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 3.671 ns fenpin200:inst21\|Add0~121 7 COMB LC_X6_Y4_N6 1 " "Info: 7: + IC(0.000 ns) + CELL(0.975 ns) = 3.671 ns; Loc. = LC_X6_Y4_N6; Fanout = 1; COMB Node = 'fenpin200:inst21\|Add0~121'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.975 ns" { fenpin200:inst21|Add0~126 fenpin200:inst21|Add0~121 } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.804 ns) 5.662 ns fenpin200:inst21\|cnt\[6\] 8 REG LC_X7_Y4_N2 5 " "Info: 8: + IC(1.187 ns) + CELL(0.804 ns) = 5.662 ns; Loc. = LC_X7_Y4_N2; Fanout = 5; REG Node = 'fenpin200:inst21\|cnt\[6\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.991 ns" { fenpin200:inst21|Add0~121 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.156 ns ( 55.74 % ) " "Info: Total cell delay = 3.156 ns ( 55.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.506 ns ( 44.26 % ) " "Info: Total interconnect delay = 2.506 ns ( 44.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.662 ns" { fenpin200:inst21|cnt[0] fenpin200:inst21|Add0~132 fenpin200:inst21|Add0~130 fenpin200:inst21|Add0~124 fenpin200:inst21|Add0~128 fenpin200:inst21|Add0~126 fenpin200:inst21|Add0~121 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.662 ns" { fenpin200:inst21|cnt[0] {} fenpin200:inst21|Add0~132 {} fenpin200:inst21|Add0~130 {} fenpin200:inst21|Add0~124 {} fenpin200:inst21|Add0~128 {} fenpin200:inst21|Add0~126 {} fenpin200:inst21|Add0~121 {} fenpin200:inst21|cnt[6] {} } { 0.000ns 1.319ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.187ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.123ns 0.261ns 0.975ns 0.804ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.118 ns" { pwm_fp_cs two_mux:inst18|dout0 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.118 ns" { pwm_fp_cs {} pwm_fp_cs~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[6] {} } { 0.000ns 0.000ns 2.869ns 0.688ns } { 0.000ns 1.132ns 0.511ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.118 ns" { pwm_fp_cs two_mux:inst18|dout0 fenpin200:inst21|cnt[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.118 ns" { pwm_fp_cs {} pwm_fp_cs~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[0] {} } { 0.000ns 0.000ns 2.869ns 0.688ns } { 0.000ns 1.132ns 0.511ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.662 ns" { fenpin200:inst21|cnt[0] fenpin200:inst21|Add0~132 fenpin200:inst21|Add0~130 fenpin200:inst21|Add0~124 fenpin200:inst21|Add0~128 fenpin200:inst21|Add0~126 fenpin200:inst21|Add0~121 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.662 ns" { fenpin200:inst21|cnt[0] {} fenpin200:inst21|Add0~132 {} fenpin200:inst21|Add0~130 {} fenpin200:inst21|Add0~124 {} fenpin200:inst21|Add0~128 {} fenpin200:inst21|Add0~126 {} fenpin200:inst21|Add0~121 {} fenpin200:inst21|cnt[6] {} } { 0.000ns 1.319ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.187ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.123ns 0.261ns 0.975ns 0.804ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pwm_from_dsc register fenpin200:inst21\|cnt\[0\] register fenpin200:inst21\|cnt\[6\] 3.629 ns " "Info: Slack time is 3.629 ns for clock \"pwm_from_dsc\" between source register \"fenpin200:inst21\|cnt\[0\]\" and destination register \"fenpin200:inst21\|cnt\[6\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "156.96 MHz 6.371 ns " "Info: Fmax is 156.96 MHz (period= 6.371 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.291 ns + Largest register register " "Info: + Largest register to register requirement is 9.291 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pwm_from_dsc 10.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"pwm_from_dsc\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pwm_from_dsc 10.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"pwm_from_dsc\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pwm_from_dsc destination 6.245 ns + Shortest register " "Info: + Shortest clock path from clock \"pwm_from_dsc\" to destination register is 6.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns pwm_from_dsc 1 CLK PIN_137 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_137; Fanout = 2; CLK Node = 'pwm_from_dsc'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm_from_dsc } "NODE_NAME" } } { "kkd.bdf" "" { Schematic "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/kkd.bdf" { { 2104 264 432 2120 "pwm_from_dsc" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.307 ns) + CELL(0.200 ns) 4.639 ns two_mux:inst18\|dout0 2 COMB LC_X7_Y4_N9 9 " "Info: 2: + IC(3.307 ns) + CELL(0.200 ns) = 4.639 ns; Loc. = LC_X7_Y4_N9; Fanout = 9; COMB Node = 'two_mux:inst18\|dout0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.507 ns" { pwm_from_dsc two_mux:inst18|dout0 } "NODE_NAME" } } { "two_mux.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/two_mux.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(0.918 ns) 6.245 ns fenpin200:inst21\|cnt\[6\] 3 REG LC_X7_Y4_N2 5 " "Info: 3: + IC(0.688 ns) + CELL(0.918 ns) = 6.245 ns; Loc. = LC_X7_Y4_N2; Fanout = 5; REG Node = 'fenpin200:inst21\|cnt\[6\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.606 ns" { two_mux:inst18|dout0 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.250 ns ( 36.03 % ) " "Info: Total cell delay = 2.250 ns ( 36.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.995 ns ( 63.97 % ) " "Info: Total interconnect delay = 3.995 ns ( 63.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.245 ns" { pwm_from_dsc two_mux:inst18|dout0 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.245 ns" { pwm_from_dsc {} pwm_from_dsc~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[6] {} } { 0.000ns 0.000ns 3.307ns 0.688ns } { 0.000ns 1.132ns 0.200ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pwm_from_dsc source 6.245 ns - Longest register " "Info: - Longest clock path from clock \"pwm_from_dsc\" to source register is 6.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns pwm_from_dsc 1 CLK PIN_137 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_137; Fanout = 2; CLK Node = 'pwm_from_dsc'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm_from_dsc } "NODE_NAME" } } { "kkd.bdf" "" { Schematic "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/kkd.bdf" { { 2104 264 432 2120 "pwm_from_dsc" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.307 ns) + CELL(0.200 ns) 4.639 ns two_mux:inst18\|dout0 2 COMB LC_X7_Y4_N9 9 " "Info: 2: + IC(3.307 ns) + CELL(0.200 ns) = 4.639 ns; Loc. = LC_X7_Y4_N9; Fanout = 9; COMB Node = 'two_mux:inst18\|dout0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.507 ns" { pwm_from_dsc two_mux:inst18|dout0 } "NODE_NAME" } } { "two_mux.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/two_mux.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(0.918 ns) 6.245 ns fenpin200:inst21\|cnt\[0\] 3 REG LC_X7_Y4_N8 4 " "Info: 3: + IC(0.688 ns) + CELL(0.918 ns) = 6.245 ns; Loc. = LC_X7_Y4_N8; Fanout = 4; REG Node = 'fenpin200:inst21\|cnt\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.606 ns" { two_mux:inst18|dout0 fenpin200:inst21|cnt[0] } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.250 ns ( 36.03 % ) " "Info: Total cell delay = 2.250 ns ( 36.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.995 ns ( 63.97 % ) " "Info: Total interconnect delay = 3.995 ns ( 63.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.245 ns" { pwm_from_dsc two_mux:inst18|dout0 fenpin200:inst21|cnt[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.245 ns" { pwm_from_dsc {} pwm_from_dsc~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[0] {} } { 0.000ns 0.000ns 3.307ns 0.688ns } { 0.000ns 1.132ns 0.200ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.245 ns" { pwm_from_dsc two_mux:inst18|dout0 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.245 ns" { pwm_from_dsc {} pwm_from_dsc~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[6] {} } { 0.000ns 0.000ns 3.307ns 0.688ns } { 0.000ns 1.132ns 0.200ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.245 ns" { pwm_from_dsc two_mux:inst18|dout0 fenpin200:inst21|cnt[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.245 ns" { pwm_from_dsc {} pwm_from_dsc~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[0] {} } { 0.000ns 0.000ns 3.307ns 0.688ns } { 0.000ns 1.132ns 0.200ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns - " "Info: - Micro setup delay of destination is 0.333 ns" {  } { { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 11 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.245 ns" { pwm_from_dsc two_mux:inst18|dout0 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.245 ns" { pwm_from_dsc {} pwm_from_dsc~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[6] {} } { 0.000ns 0.000ns 3.307ns 0.688ns } { 0.000ns 1.132ns 0.200ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.245 ns" { pwm_from_dsc two_mux:inst18|dout0 fenpin200:inst21|cnt[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.245 ns" { pwm_from_dsc {} pwm_from_dsc~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[0] {} } { 0.000ns 0.000ns 3.307ns 0.688ns } { 0.000ns 1.132ns 0.200ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.662 ns - Longest register register " "Info: - Longest register to register delay is 5.662 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fenpin200:inst21\|cnt\[0\] 1 REG LC_X7_Y4_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y4_N8; Fanout = 4; REG Node = 'fenpin200:inst21\|cnt\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { fenpin200:inst21|cnt[0] } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.319 ns) + CELL(0.747 ns) 2.066 ns fenpin200:inst21\|Add0~132 2 COMB LC_X6_Y4_N0 2 " "Info: 2: + IC(1.319 ns) + CELL(0.747 ns) = 2.066 ns; Loc. = LC_X6_Y4_N0; Fanout = 2; COMB Node = 'fenpin200:inst21\|Add0~132'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.066 ns" { fenpin200:inst21|cnt[0] fenpin200:inst21|Add0~132 } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.189 ns fenpin200:inst21\|Add0~130 3 COMB LC_X6_Y4_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.189 ns; Loc. = LC_X6_Y4_N1; Fanout = 2; COMB Node = 'fenpin200:inst21\|Add0~130'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { fenpin200:inst21|Add0~132 fenpin200:inst21|Add0~130 } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.312 ns fenpin200:inst21\|Add0~124 4 COMB LC_X6_Y4_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.312 ns; Loc. = LC_X6_Y4_N2; Fanout = 2; COMB Node = 'fenpin200:inst21\|Add0~124'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { fenpin200:inst21|Add0~130 fenpin200:inst21|Add0~124 } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.435 ns fenpin200:inst21\|Add0~128 5 COMB LC_X6_Y4_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.435 ns; Loc. = LC_X6_Y4_N3; Fanout = 2; COMB Node = 'fenpin200:inst21\|Add0~128'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { fenpin200:inst21|Add0~124 fenpin200:inst21|Add0~128 } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 2.696 ns fenpin200:inst21\|Add0~126 6 COMB LC_X6_Y4_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.261 ns) = 2.696 ns; Loc. = LC_X6_Y4_N4; Fanout = 3; COMB Node = 'fenpin200:inst21\|Add0~126'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.261 ns" { fenpin200:inst21|Add0~128 fenpin200:inst21|Add0~126 } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 3.671 ns fenpin200:inst21\|Add0~121 7 COMB LC_X6_Y4_N6 1 " "Info: 7: + IC(0.000 ns) + CELL(0.975 ns) = 3.671 ns; Loc. = LC_X6_Y4_N6; Fanout = 1; COMB Node = 'fenpin200:inst21\|Add0~121'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.975 ns" { fenpin200:inst21|Add0~126 fenpin200:inst21|Add0~121 } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.804 ns) 5.662 ns fenpin200:inst21\|cnt\[6\] 8 REG LC_X7_Y4_N2 5 " "Info: 8: + IC(1.187 ns) + CELL(0.804 ns) = 5.662 ns; Loc. = LC_X7_Y4_N2; Fanout = 5; REG Node = 'fenpin200:inst21\|cnt\[6\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.991 ns" { fenpin200:inst21|Add0~121 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "fenpin200.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin200.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.156 ns ( 55.74 % ) " "Info: Total cell delay = 3.156 ns ( 55.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.506 ns ( 44.26 % ) " "Info: Total interconnect delay = 2.506 ns ( 44.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.662 ns" { fenpin200:inst21|cnt[0] fenpin200:inst21|Add0~132 fenpin200:inst21|Add0~130 fenpin200:inst21|Add0~124 fenpin200:inst21|Add0~128 fenpin200:inst21|Add0~126 fenpin200:inst21|Add0~121 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.662 ns" { fenpin200:inst21|cnt[0] {} fenpin200:inst21|Add0~132 {} fenpin200:inst21|Add0~130 {} fenpin200:inst21|Add0~124 {} fenpin200:inst21|Add0~128 {} fenpin200:inst21|Add0~126 {} fenpin200:inst21|Add0~121 {} fenpin200:inst21|cnt[6] {} } { 0.000ns 1.319ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.187ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.123ns 0.261ns 0.975ns 0.804ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.245 ns" { pwm_from_dsc two_mux:inst18|dout0 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.245 ns" { pwm_from_dsc {} pwm_from_dsc~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[6] {} } { 0.000ns 0.000ns 3.307ns 0.688ns } { 0.000ns 1.132ns 0.200ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.245 ns" { pwm_from_dsc two_mux:inst18|dout0 fenpin200:inst21|cnt[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.245 ns" { pwm_from_dsc {} pwm_from_dsc~combout {} two_mux:inst18|dout0 {} fenpin200:inst21|cnt[0] {} } { 0.000ns 0.000ns 3.307ns 0.688ns } { 0.000ns 1.132ns 0.200ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.662 ns" { fenpin200:inst21|cnt[0] fenpin200:inst21|Add0~132 fenpin200:inst21|Add0~130 fenpin200:inst21|Add0~124 fenpin200:inst21|Add0~128 fenpin200:inst21|Add0~126 fenpin200:inst21|Add0~121 fenpin200:inst21|cnt[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.662 ns" { fenpin200:inst21|cnt[0] {} fenpin200:inst21|Add0~132 {} fenpin200:inst21|Add0~130 {} fenpin200:inst21|Add0~124 {} fenpin200:inst21|Add0~128 {} fenpin200:inst21|Add0~126 {} fenpin200:inst21|Add0~121 {} fenpin200:inst21|cnt[6] {} } { 0.000ns 1.319ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.187ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.123ns 0.261ns 0.975ns 0.804ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "dsp_clk register test_cpld_to_dsp:inst66\|now_st.D6 register test_cpld_to_dsp:inst66\|data_out\[1\] 1.1 ns " "Info: Slack time is 1.1 ns for clock \"dsp_clk\" between source register \"test_cpld_to_dsp:inst66\|now_st.D6\" and destination register \"test_cpld_to_dsp:inst66\|data_out\[1\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "112.36 MHz 8.9 ns " "Info: Fmax is 112.36 MHz (period= 8.9 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.216 ns + Largest register register " "Info: + Largest register to register requirement is 9.216 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination dsp_clk 10.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"dsp_clk\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source dsp_clk 10.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"dsp_clk\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.075 ns + Largest " "Info: + Largest clock skew is -0.075 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "dsp_clk destination 4.912 ns + Shortest register " "Info: + Shortest clock path from clock \"dsp_clk\" to destination register is 4.912 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns dsp_clk 1 CLK PIN_121 30 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_121; Fanout = 30; CLK Node = 'dsp_clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { dsp_clk } "NODE_NAME" } } { "kkd.bdf" "" { Schematic "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/kkd.bdf" { { 1992 264 432 2008 "dsp_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.862 ns) + CELL(0.918 ns) 4.912 ns test_cpld_to_dsp:inst66\|d