prev_cmp_kkd.tan.qmsg

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源码 开发软件 Quartus II

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "10 " "Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "com_to_lpt:inst2\|current_state.S2 " "Info: Detected ripple clock \"com_to_lpt:inst2\|current_state.S2\" as buffer" {  } { { "com_to_lpt.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/com_to_lpt.v" 19 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "com_to_lpt:inst2\|current_state.S2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "shift_clk:inst54\|clk_shift " "Info: Detected ripple clock \"shift_clk:inst54\|clk_shift\" as buffer" {  } { { "shift_clk.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/shift_clk.v" 5 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "shift_clk:inst54\|clk_shift" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin4:inst35\|clk_divi " "Info: Detected ripple clock \"fenpin4:inst35\|clk_divi\" as buffer" {  } { { "fenpin4.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin4.v" 3 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpin4:inst35\|clk_divi" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin4:inst34\|clk_divi " "Info: Detected ripple clock \"fenpin4:inst34\|clk_divi\" as buffer" {  } { { "fenpin4.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin4.v" 3 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpin4:inst34\|clk_divi" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "shift_clk:inst20\|clk_shift " "Info: Detected ripple clock \"shift_clk:inst20\|clk_shift\" as buffer" {  } { { "shift_clk.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/shift_clk.v" 5 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "shift_clk:inst20\|clk_shift" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "two_mux:inst18\|dout0 " "Info: Detected gated clock \"two_mux:inst18\|dout0\" as buffer" {  } { { "two_mux.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/two_mux.v" 5 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "two_mux:inst18\|dout0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin2:inst1\|clk_divi " "Info: Detected ripple clock \"fenpin2:inst1\|clk_divi\" as buffer" {  } { { "fenpin2.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin2.v" 3 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpin2:inst1\|clk_divi" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin250:inst56\|clk_divi " "Info: Detected ripple clock \"fenpin250:inst56\|clk_divi\" as buffer" {  } { { "fenpin250.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin250.v" 3 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpin250:inst56\|clk_divi" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "shift_clk:inst13\|clk_shift " "Info: Detected ripple clock \"shift_clk:inst13\|clk_shift\" as buffer" {  } { { "shift_clk.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/shift_clk.v" 5 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "shift_clk:inst13\|clk_shift" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin1000:inst55\|clk_divi " "Info: Detected ripple clock \"fenpin1000:inst55\|clk_divi\" as buffer" {  } { { "fenpin1000.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin1000.v" 3 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpin1000:inst55\|clk_divi" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK register sdi_buf:inst6\|all_cycle register dram_tmp:inst46\|code1_out\[1\] -2.856 ns " "Info: Slack time is -2.856 ns for clock \"CLK\" between source register \"sdi_buf:inst6\|all_cycle\" and destination register \"dram_tmp:inst46\|code1_out\[1\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "77.78 MHz 12.856 ns " "Info: Fmax is 77.78 MHz (period= 12.856 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.597 ns + Largest register register " "Info: + Largest register to register requirement is 1.597 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK 10.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLK\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK 10.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLK\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-7.694 ns + Largest " "Info: + Largest clock skew is -7.694 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.699 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_89 311 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_89; Fanout = 311; CLK Node = 'CLK'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "kkd.bdf" "" { Schematic "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/kkd.bdf" { { 1456 200 368 1472 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.618 ns) + CELL(0.918 ns) 3.699 ns dram_tmp:inst46\|code1_out\[1\] 2 REG LC_X6_Y6_N6 1 " "Info: 2: + IC(1.618 ns) + CELL(0.918 ns) = 3.699 ns; Loc. = LC_X6_Y6_N6; Fanout = 1; REG Node = 'dram_tmp:inst46\|code1_out\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.536 ns" { CLK dram_tmp:inst46|code1_out[1] } "NODE_NAME" } } { "dram_tmp.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/dram_tmp.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.26 % ) " "Info: Total cell delay = 2.081 ns ( 56.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.618 ns ( 43.74 % ) " "Info: Total interconnect delay = 1.618 ns ( 43.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { CLK dram_tmp:inst46|code1_out[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { CLK {} CLK~combout {} dram_tmp:inst46|code1_out[1] {} } { 0.000ns 0.000ns 1.618ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 11.393 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 11.393 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_89 311 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_89; Fanout = 311; CLK Node = 'CLK'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "kkd.bdf" "" { Schematic "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/kkd.bdf" { { 1456 200 368 1472 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.618 ns) + CELL(1.294 ns) 4.075 ns fenpin2:inst1\|clk_divi 2 REG LC_X12_Y5_N0 20 " "Info: 2: + IC(1.618 ns) + CELL(1.294 ns) = 4.075 ns; Loc. = LC_X12_Y5_N0; Fanout = 20; REG Node = 'fenpin2:inst1\|clk_divi'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.912 ns" { CLK fenpin2:inst1|clk_divi } "NODE_NAME" } } { "fenpin2.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin2.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.070 ns) + CELL(1.294 ns) 7.439 ns fenpin1000:inst55\|clk_divi 3 REG LC_X12_Y3_N5 226 " "Info: 3: + IC(2.070 ns) + CELL(1.294 ns) = 7.439 ns; Loc. = LC_X12_Y3_N5; Fanout = 226; REG Node = 'fenpin1000:inst55\|clk_divi'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.364 ns" { fenpin2:inst1|clk_divi fenpin1000:inst55|clk_divi } "NODE_NAME" } } { "fenpin1000.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fenpin1000.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.036 ns) + CELL(0.918 ns) 11.393 ns sdi_buf:inst6\|all_cycle 4 REG LC_X6_Y8_N9 1 " "Info: 4: + IC(3.036 ns) + CELL(0.918 ns) = 11.393 ns; Loc. = LC_X6_Y8_N9; Fanout = 1; REG Node = 'sdi_buf:inst6\|all_cycle'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.954 ns" { fenpin1000:inst55|clk_divi sdi_buf:inst6|all_cycle } "NODE_NAME" } } { "sdi_buf.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/sdi_buf.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 40.98 % ) " "Info: Total cell delay = 4.669 ns ( 40.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.724 ns ( 59.02 % ) " "Info: Total interconnect delay = 6.724 ns ( 59.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.393 ns" { CLK fenpin2:inst1|clk_divi fenpin1000:inst55|clk_divi sdi_buf:inst6|all_cycle } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.393 ns" { CLK {} CLK~combout {} fenpin2:inst1|clk_divi {} fenpin1000:inst55|clk_divi {} sdi_buf:inst6|all_cycle {} } { 0.000ns 0.000ns 1.618ns 2.070ns 3.036ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { CLK dram_tmp:inst46|code1_out[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { CLK {} CLK~combout {} dram_tmp:inst46|code1_out[1] {} } { 0.000ns 0.000ns 1.618ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.393 ns" { CLK fenpin2:inst1|clk_divi fenpin1000:inst55|clk_divi sdi_buf:inst6|all_cycle } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.393 ns" { CLK {} CLK~combout {} fenpin2:inst1|clk_divi {} fenpin1000:inst55|clk_divi {} sdi_buf:inst6|all_cycle {} } { 0.000ns 0.000ns 1.618ns 2.070ns 3.036ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "sdi_buf.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/sdi_buf.v" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns - " "Info: - Micro setup delay of destination is 0.333 ns" {  } { { "dram_tmp.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/dram_tmp.v" 68 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { CLK dram_tmp:inst46|code1_out[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { CLK {} CLK~combout {} dram_tmp:inst46|code1_out[1] {} } { 0.000ns 0.000ns 1.618ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.393 ns" { CLK fenpin2:inst1|clk_divi fenpin1000:inst55|clk_divi sdi_buf:inst6|all_cycle } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.393 ns" { CLK {} CLK~combout {} fenpin2:inst1|clk_divi {} fenpin1000:inst55|clk_divi {} sdi_buf:inst6|all_cycle {} } { 0.000ns 0.000ns 1.618ns 2.070ns 3.036ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.453 ns - Longest register register " "Info: - Longest register to register delay is 4.453 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sdi_buf:inst6\|all_cycle 1 REG LC_X6_Y8_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y8_N9; Fanout = 1; REG Node = 'sdi_buf:inst6\|all_cycle'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { sdi_buf:inst6|all_cycle } "NODE_NAME" } } { "sdi_buf.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/sdi_buf.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.595 ns) 0.595 ns dram_tmp:inst46\|position_out\[31\]~330 2 COMB LC_X6_Y8_N9 96 " "Info: 2: + IC(0.000 ns) + CELL(0.595 ns) = 0.595 ns; Loc. = LC_X6_Y8_N9; Fanout = 96; COMB Node = 'dram_tmp:inst46\|position_out\[31\]~330'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.595 ns" { sdi_buf:inst6|all_cycle dram_tmp:inst46|position_out[31]~330 } "NODE_NAME" } } { "dram_tmp.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/dram_tmp.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.615 ns) + CELL(1.243 ns) 4.453 ns dram_tmp:inst46\|code1_out\[1\] 3 REG LC_X6_Y6_N6 1 " "Info: 3: + IC(2.615 ns) + CELL(1.243 ns) = 4.453 ns; Loc. = LC_X6_Y6_N6; Fanout = 1; REG Node = 'dram_tmp:inst46\|code1_out\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.858 ns" { dram_tmp:inst46|position_out[31]~330 dram_tmp:inst46|code1_out[1] } "NODE_NAME" } } { "dram_tmp.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/dram_tmp.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.838 ns ( 41.28 % ) " "Info: Total cell delay = 1.838 ns ( 41.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.615 ns ( 58.72 % ) " "Info: Total interconnect delay = 2.615 ns ( 58.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.453 ns" { sdi_buf:inst6|all_cycle dram_tmp:inst46|position_out[31]~330 dram_tmp:inst46|code1_out[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.453 ns" { sdi_buf:inst6|all_cycle {} dram_tmp:inst46|position_out[31]~330 {} dram_tmp:inst46|code1_out[1] {} } { 0.000ns 0.000ns 2.615ns } { 0.000ns 0.595ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { CLK dram_tmp:inst46|code1_out[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { CLK {} CLK~combout {} dram_tmp:inst46|code1_out[1] {} } { 0.000ns 0.000ns 1.618ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.393 ns" { CLK fenpin2:inst1|clk_divi fenpin1000:inst55|clk_divi sdi_buf:inst6|all_cycle } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.393 ns" { CLK {} CLK~combout {} fenpin2:inst1|clk_divi {} fenpin1000:inst55|clk_divi {} sdi_buf:inst6|all_cycle {} } { 0.000ns 0.000ns 1.618ns 2.070ns 3.036ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.453 ns" { sdi_buf:inst6|all_cycle dram_tmp:inst46|position_out[31]~330 dram_tmp:inst46|code1_out[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.453 ns" { sdi_buf:inst6|all_cycle {} dram_tmp:inst46|position_out[31]~330 {} dram_tmp:inst46|code1_out[1] {} } { 0.000ns 0.000ns 2.615ns } { 0.000ns 0.595ns 1.243ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'CLK' 145 " "Warning: Can't achieve timing requirement Clock Setup: 'CLK' along 145 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 0}