prev_cmp_kkd.map.qmsg

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源码 开发软件 Quartus II

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Web Edition " "Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 17 09:03:22 2008 " "Info: Processing started: Wed Sep 17 09:03:22 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off kkd -c kkd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off kkd -c kkd" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "kkd.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file kkd.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 kkd " "Info: Found entity 1: kkd" {  } { { "kkd.bdf" "" { Schematic "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/kkd.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "com_to_lpt.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file com_to_lpt.v" { { "Info" "ISGN_ENTITY_NAME" "1 com_to_lpt " "Info: Found entity 1: com_to_lpt" {  } { { "com_to_lpt.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/com_to_lpt.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "D_trigger.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file D_trigger.v" { { "Info" "ISGN_ENTITY_NAME" "1 D_trigger " "Info: Found entity 1: D_trigger" {  } { { "D_trigger.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/D_trigger.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fw_delay.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fw_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 fw_delay " "Info: Found entity 1: fw_delay" {  } { { "fw_delay.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/fw_delay.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "JK_trigger.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file JK_trigger.v" { { "Info" "ISGN_ENTITY_NAME" "1 JK_trigger " "Info: Found entity 1: JK_trigger" {  } { { "JK_trigger.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/JK_trigger.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "modu4.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file modu4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 modu4 " "Info: Found entity 1: modu4" {  } { { "modu4.bdf" "" { Schematic "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/modu4.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "modu5.v(12) " "Warning (10268): Verilog HDL information at modu5.v(12): always construct contains both blocking and non-blocking assignments" {  } { { "modu5.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/modu5.v" 12 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "modu5.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file modu5.v" { { "Info" "ISGN_ENTITY_NAME" "1 modu5 " "Info: Found entity 1: modu5" {  } { { "modu5.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/modu5.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mux2.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux2 " "Info: Found entity 1: mux2" {  } { { "mux2.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/mux2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qei_filter.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file qei_filter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 qei_filter " "Info: Found entity 1: qei_filter" {  } { { "qei_filter.bdf" "" { Schematic "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/qei_filter.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qei_top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file qei_top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 qei_top " "Info: Found entity 1: qei_top" {  } { { "qei_top.bdf" "" { Schematic "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/qei_top.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdi_buf.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdi_buf.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdi_buf " "Info: Found entity 1: sdi_buf" {  } { { "sdi_buf.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/sdi_buf.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "send_to_dsp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file send_to_dsp.v" { { "Info" "ISGN_ENTITY_NAME" "1 send_to_dsp " "Info: Found entity 1: send_to_dsp" {  } { { "send_to_dsp.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/send_to_dsp.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sent_buf.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sent_buf.v" { { "Info" "ISGN_ENTITY_NAME" "1 sent_buf " "Info: Found entity 1: sent_buf" {  } { { "sent_buf.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/sent_buf.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shift_clk.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file shift_clk.v" { { "Info" "ISGN_ENTITY_NAME" "1 shift_clk " "Info: Found entity 1: shift_clk" {  } { { "shift_clk.v" "" { Text "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/shift_clk.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "xx4x.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file xx4x.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 xx4x " "Info: Found entity 1: xx4x" {  } { { "xx4x.bdf" "" { Schematic "F:/suns_gongsi/for_extent/test_cpld_1/test_cpld/xx4x.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}