fw_delay.v

来自「基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源」· Verilog 代码 · 共 27 行

module fw_delay(clk_ref,rst,norm);
input     clk_ref;
input     norm;
output    rst;
reg       rst;
reg[9:0]  tep1;  

always @(posedge clk_ref or negedge norm)
begin
if(!norm)
    begin
    tep1<=10'b0;
    rst<=1'b0;
    end
else if(tep1>=10'b1100100000)       //上电100ms复位有效
    begin
    rst<=1'b1;
    tep1<=tep1;
    end
else
    begin
    tep1<=tep1+10'b0000000001;
    rst<=1'b0;
    end
end

endmodule