dram.v

来自「基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源」· Verilog 代码 · 共 71 行

module DRAM(rst,clk,ad_over,ad_lz,ad_zx,ad_hx,code1_in,code2_in,pwm_in,ad_lz_out,ad_zx_out,ad_hx_out,code1_out,code2_out,pwm_out);
input        rst;
input        clk;
input        ad_over;
input[23:0]  ad_lz;
input[23:0]  ad_zx;
input[23:0]  ad_hx;
input[31:0]  code1_in;
input[31:0]  code2_in;
input[31:0]  pwm_in;
output[23:0] ad_lz_out;
output[23:0] ad_zx_out;
output[23:0] ad_hx_out;
output[31:0] code1_out;
output[31:0] code2_out;
output[31:0] pwm_out;
reg[23:0]    ad_lz_out;
reg[23:0]    ad_zx_out;
reg[23:0]    ad_hx_out;
reg[31:0]    code1_out;
reg[31:0]    code2_out;
reg[31:0]    pwm_out;
reg          inn1;
reg          inn2;

always @(posedge clk or negedge rst)
begin
if(!rst)
   begin
   inn1<=1'b0;
   inn2<=1'b0;
   end
else
   begin
   inn1<=ad_over;
   inn2<=inn1;
   end
end

always @(posedge clk or negedge rst)
begin
if(!rst)
begin
  ad_lz_out<=24'b0;
  ad_zx_out<=24'b0;
  ad_hx_out<=24'b0;
  code1_out<=32'b0;
  code2_out<=32'b0;
  pwm_out<=32'b0;
end
else if(inn1!=inn2)
  begin
  ad_lz_out<=ad_lz;
  ad_zx_out<=ad_zx;
  ad_hx_out<=ad_hx;
  code1_out<=code1_in;
  code2_out<=code2_in;
  pwm_out<=pwm_in;   
  end
else
  begin
  ad_lz_out<=ad_lz_out;
  ad_zx_out<=ad_zx_out;
  ad_hx_out<=ad_hx_out;
  code1_out<=code1_out;
  code2_out<=code2_out;
  pwm_out<=pwm_out; 
  end
end

endmodule