kkd.qsf

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源码 开发软件 Quartus II

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		kkd_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EPM1270T144C5
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name TOP_LEVEL_ENTITY kkd
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:38:04  AUGUST 03, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT ANY
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name BDF_FILE kkd.bdf
set_global_assignment -name VERILOG_FILE com_to_lpt.v
set_global_assignment -name VERILOG_FILE D_trigger.v
set_global_assignment -name VERILOG_FILE fw_delay.v
set_global_assignment -name VERILOG_FILE JK_trigger.v
set_global_assignment -name BDF_FILE modu4.bdf
set_global_assignment -name VERILOG_FILE modu5.v
set_global_assignment -name VERILOG_FILE mux2.v
set_global_assignment -name BDF_FILE qei_filter.bdf
set_global_assignment -name BDF_FILE qei_top.bdf
set_global_assignment -name VERILOG_FILE sdi_buf.v
set_global_assignment -name VERILOG_FILE send_to_dsp.v
set_global_assignment -name VERILOG_FILE sent_buf.v
set_global_assignment -name VERILOG_FILE shift_clk.v
set_global_assignment -name BDF_FILE xx4x.bdf
set_global_assignment -name BDF_FILE xx704x.bdf
set_global_assignment -name BDF_FILE xx164x.bdf
set_global_assignment -name BDF_FILE xx165x.bdf
set_global_assignment -name BDF_FILE X704X.bdf
set_global_assignment -name VERILOG_FILE two_mux.v
set_location_assignment PIN_89 -to CLK
set_location_assignment PIN_122 -to cs
set_location_assignment PIN_133 -to dsp[1]
set_location_assignment PIN_132 -to dsp[2]
set_location_assignment PIN_131 -to dsp[3]
set_location_assignment PIN_130 -to dsp[4]
set_location_assignment PIN_127 -to dsp[5]
set_location_assignment PIN_125 -to dsp[6]
set_location_assignment PIN_124 -to dsp[7]
set_location_assignment PIN_123 -to dsp[8]
set_location_assignment PIN_121 -to dsp_clk
set_location_assignment PIN_142 -to norm
set_location_assignment PIN_106 -to SCLK0
set_location_assignment PIN_107 -to SDI0
set_location_assignment PIN_108 -to SDO0
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
set_global_assignment -name VECTOR_WAVEFORM_FILE kkd.vwf
set_global_assignment -name FMAX_REQUIREMENT "100 MHz"
set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id clk
set_instance_assignment -name CLOCK_SETTINGS clk -to CLK
set_global_assignment -name BDF_FILE filer.bdf
set_global_assignment -name VERILOG_FILE fy12.v
set_global_assignment -name VERILOG_FILE fenpin2.v
set_global_assignment -name BDF_FILE divi.bdf
set_global_assignment -name VERILOG_FILE fenpin4.v
set_global_assignment -name VERILOG_FILE fenpin1000.v
set_location_assignment PIN_119 -to dsp_ck
set_global_assignment -name VERILOG_FILE fenpin500.v
set_global_assignment -name VERILOG_FILE fenpin250.v
set_global_assignment -name VERILOG_FILE pwm_counter.v
set_global_assignment -name VERILOG_FILE fenpin100.v
set_global_assignment -name VERILOG_FILE fenpin1024.v
set_global_assignment -name VECTOR_WAVEFORM_FILE test_cpld.vwf
set_global_assignment -name VERILOG_FILE DRAM.v
set_location_assignment PIN_144 -to interrupt_call
set_global_assignment -name VERILOG_FILE clk_inter.v
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name VERILOG_FILE test_cpld_to_dsp.v
set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id clk_dsp
set_instance_assignment -name CLOCK_SETTINGS clk_dsp -to dsp_clk
set_global_assignment -name VERILOG_FILE trig_two_to_one.v
set_global_assignment -name VERILOG_FILE dram_tmp.v
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name VERILOG_FILE fenpin200.v
set_location_assignment PIN_134 -to pwm_fp_cs
set_location_assignment PIN_137 -to pwm_from_dsc
set_location_assignment PIN_120 -to pwm_out
set_location_assignment PIN_14 -to pwm_sign
set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id pwm_clk
set_instance_assignment -name CLOCK_SETTINGS pwm_clk -to pwm_from_dsc
set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id cs_clk
set_instance_assignment -name CLOCK_SETTINGS cs_clk -to pwm_fp_cs
set_global_assignment -name BDF_FILE xw_filter.bdf
set_global_assignment -name VERILOG_FILE limit_data.v
set_location_assignment PIN_20 -to xw_up
set_location_assignment PIN_30 -to xw_down
set_global_assignment -name VERILOG_FILE sdi_buf0.v
set_location_assignment PIN_103 -to SCLK1
set_location_assignment PIN_104 -to SDI1
set_location_assignment PIN_117 -to qea1
set_location_assignment PIN_118 -to qea2
set_location_assignment PIN_113 -to qeb1
set_location_assignment PIN_114 -to qeb2
set_location_assignment PIN_129 -to qei_clr
set_global_assignment -name VERILOG_FILE xw_logic.v
set_global_assignment -name BDF_FILE position_moudle.bdf
set_global_assignment -name VERILOG_FILE posi.v
set_location_assignment PIN_11 -to wy_clr
set_location_assignment PIN_31 -to wy_qea
set_location_assignment PIN_32 -to wy_qeb
set_location_assignment PIN_1 -to wy_not
set_location_assignment PIN_3 -to aa
set_location_assignment PIN_4 -to bb
set_location_assignment PIN_12 -to pwm_mirror
set_location_assignment PIN_105 -to SDO1
set_location_assignment PIN_98 -to SCLK2
set_location_assignment PIN_101 -to SDI2
set_location_assignment PIN_102 -to sdo2
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"