stp1.stp

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源码 开发软件 Quartus II

<session jtag_chain="ByteBlasterII [LPT1]" jtag_device="@1: EPM1270 (0x020A30DD)" sof_file="" top_level_entity="kkd">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <global_info>
    <multi attribute="window position" size="9" value="732,408,398,130,356,50,100,0,5"/>
    <single attribute="active instance" value="0"/>
    <single attribute="lock mode" value="36110"/>
  </global_info>
  <instance compilation_mode="incremental" entity_name="sld_signaltap" is_auto_node="yes" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="5"/>
    <position_info>
      <single attribute="active tab" value="1"/>
    </position_info>
    <signal_set global_temp="1" name="signal_set: 2007/12/17 18:52:47  #0">
      <clock name="CLK" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="yes" trigger_in_node="dsp_clk" trigger_out_enable="no" trigger_out_pin="auto_stp_trigger_out_0"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire name="dram_tmp:inst11|inn1" tap_mode="probeonly" type="register"/>
          <wire name="dram_tmp:inst11|inn2" tap_mode="probeonly" type="register"/>
          <wire name="dsp_clk" tap_mode="probeonly" type="input pin"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire name="dram_tmp:inst11|inn1" tap_mode="probeonly" type="register"/>
          <wire name="dram_tmp:inst11|inn2" tap_mode="probeonly" type="register"/>
          <wire name="dsp_clk" tap_mode="probeonly" type="input pin"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <net is_signal_inverted="no" name="dsp_clk"/>
          <net is_signal_inverted="no" name="dram_tmp:inst11|inn1"/>
          <net is_signal_inverted="no" name="dram_tmp:inst11|inn2"/>
        </data_view>
        <setup_view>
          <net is_signal_inverted="no" name="dsp_clk"/>
          <net is_signal_inverted="no" name="dram_tmp:inst11|inn1"/>
          <net is_signal_inverted="no" name="dram_tmp:inst11|inn2"/>
        </setup_view>
      </presentation>
      <trigger global_temp="1" name="trigger: 2007/12/17 18:52:47  #1" position="pre" power_up_trigger_mode="false" segment_size="1" trigger_in="rising edge" trigger_out="active high" trigger_type="circular">
        <power_up_trigger position="pre" segment_size="1" trigger_in="dont_care" trigger_out="active high" trigger_type="circular"/>
        <events>
          <level enabled="yes" type="basic">
            <power_up enabled="yes">
            </power_up>
            <op_node/>
          </level>
        </events>
      </trigger>
    </signal_set>
  </instance>
  <mnemonics/>
</session>