clk_inter.v

来自「基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源」· Verilog 代码 · 共 42 行

module clk_inter(clkk,rst,call_intr);
input     clkk;
input     rst;
output    call_intr;
reg       call_intr;

//always @(posedge clkk or negedge rst)
//begin
//if(!rst)
//begin
//clkcc<=6'b0;
//call_intr<=1'b0;
//end
//else if(vvoo==1'b1)
//    begin
//    if(clkcc==6'b100111)
//       begin
//       clkcc<=6'b0;
//       call_intr<=~call_intr;
//       end
//    else
//       begin
//       clkcc<=clkcc+6'b000001;
//       call_intr<=call_intr;
//       end
//    end
//else
//begin
//clkcc<=6'b0;
//call_intr<=call_intr;
//end
//end

always @(posedge clkk or negedge rst)
begin
if(!rst)
call_intr<=1'b0;
else 
call_intr<=~call_intr;
end

endmodule