📄 trig_two_to_one.v
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module trig_two_to_one(clk,rst,interrupt_sign,interrupt_beg);
input clk;
input rst;
input interrupt_sign;
output interrupt_beg;
reg interrupt_beg;
reg cc1;
reg cc2;
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
cc1<=1'b0;
cc2<=1'b0;
end
else
begin
cc1<=interrupt_sign;
cc2<=cc1;
end
end
always @(posedge clk or negedge rst)
begin
if(!rst)
interrupt_beg<=1'b0;
else if(cc1!=cc2)
interrupt_beg<=~interrupt_beg;
else
interrupt_beg<=interrupt_beg;
end
endmodule
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