sdi_buf0.v

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源码 开发软件 Quartus II

module sdi_buf0(clk,rst,sdi_set,clk_control,plt_in,ad_data);
input         clk,rst;
input[31:0]   plt_in;
input         sdi_set;
output        clk_control;
output[23:0]  ad_data;
reg           clk_control;
reg[23:0]     ad_data;
reg[23:0]     tem;
reg           shat;
reg           fa;
reg           tr;
reg[5:0]      clkc;

always @(posedge clk or negedge rst)
begin
if(!rst)
   begin
   shat<=1'b0;
   fa<=1'b0;
   tr<=1'b1;
   clk_control<=1'b0;
   end
else if(sdi_set==1'b0)
   begin
       if(shat==1'b0)
       begin
       tr<=1'b1;
       fa<=1'b1;
       shat<=1'b1;
       clk_control<=1'b1;
       end
       else if(clkc==6'b100111)
            begin
            tr<=1'b0;
            fa<=tr;
            shat<=1'b0;
            clk_control<=1'b0;
            end
       else
            begin
            if(!tr)
            tr<=1'b0;
            else
            begin
            tr<=1'b1;
            end
            if(!fa)
            fa<=1'b0;
            else
            begin
            fa<=1'b1;
            end
            shat<=shat;
            clk_control<=clk_control;
            end
   end
else if(shat==1'b1)
   begin
   if(clkc==6'b100111)
       begin
       tr<=1'b0;
       fa<=tr;
       shat<=1'b0;
       clk_control<=1'b0;
       end
   else
       begin
       if(!tr)
       tr<=1'b0;
       else
       begin
       tr<=1'b1;
       end
       if(!fa)
       fa<=1'b0;
       else
       begin
       fa<=1'b1;
       end
       shat<=shat;
       clk_control<=clk_control;
       end
   end
else
   begin
       if(!tr)
       tr<=1'b0;
       else
       begin
       tr<=1'b1;
       end
       if(!fa)
       fa<=1'b0;
       else
       begin
       fa<=1'b1;
       end
   shat<=shat;
   clk_control<=clk_control;
   end
end

always @(posedge clk or negedge rst)
begin
if(!rst)
begin
ad_data<=24'b0;
tem<=24'b0;
end
else if(shat==1'b0)
  begin
     if(fa==1'b1)
       begin
       ad_data<=plt_in[31:8];
       tem<=plt_in[31:8];
       end
     else
       ad_data<=tem;
  end
else
ad_data<=tem;
end

always @(posedge clk or negedge rst)
begin
if(!rst)
  clkc<=6'b0;
else if(clkc==6'b100111)
  clkc<=6'b0;
else if(shat==1'b1)
  clkc<=clkc+6'b000001;
else
  clkc<=6'b0;
end

endmodule