pwm_counter.v

来自「基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源」· Verilog 代码 · 共 32 行

module pwm_counter(clk,pwm_in,rst,sign,clr,pwm_out);
input	     clk;
input        pwm_in;
input        rst;
input        sign;
input        clr;
output[31:0] pwm_out;
reg[31:0]    pwm_out1;
reg[31:0]    pwm_out;

always @(posedge clk or negedge rst)
begin
if(!rst)
pwm_out<=32'h00000000;
else
pwm_out<=pwm_out1;
end

always @(posedge pwm_in or negedge clr)
begin
if(!clr)
pwm_out1<=32'h00000000;
else
begin
if(sign==1'b0)
pwm_out1<=pwm_out1+32'h00000001;
else
pwm_out1<=pwm_out1-32'h00000001;
end
end

endmodule