xw_logic.v

来自「基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源」· Verilog 代码 · 共 32 行

module xw_logic(pwm_i,up_stop,down_stop,mot_sign,pwm_driver);
input pwm_i;
input up_stop;
input down_stop;
input mot_sign;
output pwm_driver;
reg    pwm_driver;
reg[1:0] ttp;

always @(pwm_i or up_stop or down_stop or mot_sign)
begin
ttp<={up_stop,down_stop};
case(ttp)
    2'b00: pwm_driver<=1'b0;
    2'b01: begin
           if(mot_sign==1'b0)
           pwm_driver<=1'b0;
           else
           pwm_driver<=pwm_i;
           end
    2'b10: begin
           if(mot_sign==1'b0)
           pwm_driver<=pwm_i; 
           else
           pwm_driver<=1'b0;           
           end
    2'b11: pwm_driver<=pwm_i;
  default: pwm_driver<=1'b0;
endcase
end

endmodule