fenpin1000.v

来自「基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源」· Verilog 代码 · 共 27 行

module fenpin1000(clk,rst,clk_divi);
input    clk,rst;
output   clk_divi;
reg      clk_divi;
reg[9:0] cnt;

always @(posedge clk or negedge rst)
begin
if(!rst)
cnt<=10'b0;
else if(cnt==10'b1111100111)
cnt<=10'b0;
else
cnt<=cnt+10'b0000000001;
end

always @(posedge clk or negedge rst)
begin
if(!rst)
clk_divi<=1'b0;
else if(cnt>10'b0111110011)
clk_divi<=1'b1;
else
clk_divi<=1'b0;
end

endmodule